44 lines
1.4 KiB
Systemverilog
44 lines
1.4 KiB
Systemverilog
interface axi4_if #(
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parameter int unsigned ADDR_W = 32,
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parameter int unsigned DATA_W = 32,
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parameter int unsigned ID_W = 4,
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parameter int unsigned USER_W = 1
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)(
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input logic aclk,
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input logic aresetn
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);
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import axi_pkg::*;
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typedef logic [ADDR_W-1:0] addr_t;
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typedef logic [DATA_W-1:0] data_t;
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typedef logic [DATA_W/8-1:0] strb_t;
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typedef logic [ID_W-1:0] id_t;
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typedef logic [USER_W-1:0] user_t;
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`AXI4_TYPEDEF_ALL(axi, addr_t, data_t, strb_t, id_t, user_t);
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axi_req_t req;
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axi_resp_t resp;
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modport master (input aclk, aresetn, output req, input resp);
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modport slave (input aclk, aresetn, input req, output resp);
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modport monitor(input aclk, aresetn, input req, input resp);
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endinterface : axi4_if
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interface axi4l_if #(
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parameter int unsigned ADDR_W = 32,
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parameter int unsigned DATA_W = 32,
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parameter int unsigned USER_W = 1
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)(
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input logic aclk,
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input logic aresetn
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);
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import axi_pkg::*;
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typedef logic [ADDR_W-1:0] addr_t;
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typedef logic [DATA_W-1:0] data_t;
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typedef logic [DATA_W/8-1:0] strb_t;
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typedef logic [USER_W-1:0] user_t;
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`AXI4L_TYPEDEF_ALL(axil, addr_t, data_t, strb_t, user_t);
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axil_req_t req;
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axil_resp_t resp;
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modport master (input aclk, aresetn, output req, input resp);
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modport slave (input aclk, aresetn, input req, output resp);
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modport monitor(input aclk, aresetn, input req, input resp);
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endinterface : axi4l_if
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