309 lines
15 KiB
Systemverilog
309 lines
15 KiB
Systemverilog
module axi_dma_wrapper #(
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parameter AXI_DATA_WIDTH = 32,
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parameter AXI_ADDR_WIDTH = 16,
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parameter AXI_ID_WIDTH = 8,
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parameter AXI_MAX_BURST_LEN = 16,
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parameter AXIS_LAST_ENABLE = 1,
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parameter AXIS_ID_ENABLE = 0,
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parameter AXIS_ID_WIDTH = 8,
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parameter AXIS_DEST_ENABLE = 0,
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parameter AXIS_DEST_WIDTH = 8,
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parameter AXIS_USER_ENABLE = 1,
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parameter AXIS_USER_WIDTH = 1,
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parameter LEN_WIDTH = 20,
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parameter TAG_WIDTH = 8,
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parameter ENABLE_SG = 0,
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parameter ENABLE_UNALIGNED = 0
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)(
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input wire crossbar_clk,
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input wire crossbar_rst,
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input wire dma_clk,
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input wire dma_rst,
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axi4l_if.slave s_axil_control,
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axi4_if.master m_axi_data,
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output wire [AXIS_DATA_WIDTH-1:0] m_axis_read_data_tdata,
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output wire [AXIS_KEEP_WIDTH-1:0] m_axis_read_data_tkeep,
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output wire m_axis_read_data_tvalid,
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input wire m_axis_read_data_tready,
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output wire m_axis_read_data_tlast,
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output wire [AXIS_ID_WIDTH-1:0] m_axis_read_data_tid,
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output wire [AXIS_DEST_WIDTH-1:0] m_axis_read_data_tdest,
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output wire [AXIS_USER_WIDTH-1:0] m_axis_read_data_tuser,
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input wire [AXIS_DATA_WIDTH-1:0] s_axis_write_data_tdata,
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input wire [AXIS_KEEP_WIDTH-1:0] s_axis_write_data_tkeep,
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input wire s_axis_write_data_tvalid,
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output wire s_axis_write_data_tready,
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input wire s_axis_write_data_tlast,
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input wire [AXIS_ID_WIDTH-1:0] s_axis_write_data_tid,
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input wire [AXIS_DEST_WIDTH-1:0] s_axis_write_data_tdest,
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input wire [AXIS_USER_WIDTH-1:0] s_axis_write_data_tuser
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);
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wire [AXI_ADDR_WIDTH-1:0] dma_s_axis_read_desc_addr;
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wire [LEN_WIDTH-1:0] dma_s_axis_read_desc_len;
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wire [TAG_WIDTH-1:0] dma_s_axis_read_desc_tag;
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wire [AXIS_ID_WIDTH-1:0] dma_s_axis_read_desc_id;
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wire [AXIS_DEST_WIDTH-1:0] dma_s_axis_read_desc_dest;
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wire [AXIS_USER_WIDTH-1:0] dma_s_axis_read_desc_user;
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wire dma_s_axis_read_desc_valid;
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wire dma_s_axis_read_desc_ready;
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wire [TAG_WIDTH-1:0] dma_m_axis_read_desc_status_tag;
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wire [3:0] dma_m_axis_read_desc_status_error;
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wire dma_m_axis_read_desc_status_valid;
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wire [AXI_ID_WIDTH-1:0] dma_m_axi_awid;
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wire [AXI_ADDR_WIDTH-1:0] dma_m_axi_awaddr;
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wire [7:0] dma_m_axi_awlen;
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wire [2:0] dma_m_axi_awsize;
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wire [1:0] dma_m_axi_awburst;
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wire dma_m_axi_awlock;
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wire [3:0] dma_m_axi_awcache;
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wire [2:0] dma_m_axi_awprot;
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wire dma_m_axi_awvalid;
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wire dma_m_axi_awready;
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wire [AXI_DATA_WIDTH-1:0] dma_m_axi_wdata;
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wire [AXI_STRB_WIDTH-1:0] dma_m_axi_wstrb;
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wire dma_m_axi_wlast;
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wire dma_m_axi_wvalid;
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wire dma_m_axi_wready;
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wire [AXI_ID_WIDTH-1:0] dma_m_axi_bid;
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wire [1:0] dma_m_axi_bresp;
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wire dma_m_axi_bvalid;
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wire dma_m_axi_bready;
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wire [AXI_ID_WIDTH-1:0] dma_m_axi_arid;
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wire [AXI_ADDR_WIDTH-1:0] dma_m_axi_araddr;
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wire [7:0] dma_m_axi_arlen;
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wire [2:0] dma_m_axi_arsize;
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wire [1:0] dma_m_axi_arburst;
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wire dma_m_axi_arlock;
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wire [3:0] dma_m_axi_arcache;
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wire [2:0] dma_m_axi_arprot;
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wire dma_m_axi_arvalid;
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wire dma_m_axi_arready;
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wire [AXI_ID_WIDTH-1:0] dma_m_axi_rid;
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wire [AXI_DATA_WIDTH-1:0] dma_m_axi_rdata;
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wire [1:0] dma_m_axi_rresp;
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wire dma_m_axi_rlast;
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wire dma_m_axi_rvalid;
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wire dma_m_axi_rready;
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wire [AXI_ADDR_WIDTH-1:0] dma_s_axis_write_desc_addr;
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wire [LEN_WIDTH-1:0] dma_s_axis_write_desc_len;
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wire [TAG_WIDTH-1:0] dma_s_axis_write_desc_tag;
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wire dma_s_axis_write_desc_valid;
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wire dma_s_axis_write_desc_ready;
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wire [LEN_WIDTH-1:0] dma_m_axis_write_desc_status_len;
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wire [TAG_WIDTH-1:0] dma_m_axis_write_desc_status_tag;
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wire [AXIS_ID_WIDTH-1:0] dma_m_axis_write_desc_status_id;
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wire [AXIS_DEST_WIDTH-1:0] dma_m_axis_write_desc_status_dest;
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wire [AXIS_USER_WIDTH-1:0] dma_m_axis_write_desc_status_user;
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wire [3:0] dma_m_axis_write_desc_status_error;
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wire dma_m_axis_write_desc_status_valid;
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wire dma_read_enable;
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wire dma_write_enable;
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wire dma_write_abort;
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axi4l_if #(.ADDR_W(AXI_ADDR_WIDTH), .DATA_W(AXI_DATA_WIDTH)) axi4_if_cdc ();
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axil_cdc_wrapper #(
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.ADDR_WIDTH (AXI_ADDR_WIDTH),
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.DATA_WIDTH (AXI_DATA_WIDTH)
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) i_dma_ctrl_cdc (
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.s_clk (crossbar_clk),
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.s_rst (crossbar_rst),
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.s_axi (s_axil_control),
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.m_clk (dma_clk),
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.m_rst (dma_rst),
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.m_axi (axi4_if_cdc)
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);
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wire [N_REGS-1:0][31:0] reg_i;
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wire [N_REGS-1:0][31:0] reg_o;
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import dma_axil_reg_map_pkg::*;
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axi4l_reg_map #(
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.ADDR_W (AXI_ADDR_WIDTH),
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.DATA_W (AXI_DATA_WIDTH),
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.USER_W (0),
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.N_REGS (DMA_AXIL_REG_MAP_N_REGS),
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.REG_MODE (DMA_AXIL_REG_MAP_REG_MODE),
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.REG_RST (DMA_AXIL_REG_MAP_REG_RST)
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) i_axi4l_dma_reg_map (
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.clk (dma_clk),
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.rst_n (!dma_rst),
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.s_axil (axi4_if_cdc),
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.reg_i (reg_i),
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.reg_o (reg_o)
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);
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always_comb begin
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dma_s_axis_write_desc_valid = reg_o[DMA_WRITE_DESC_CONTROL_REG][0];
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dma_s_axis_write_desc_addr = reg_o[DMA_WRITE_DESC_ADDR_REG][31:0];
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dma_s_axis_write_desc_len = reg_o[DMA_WRITE_DESC_LEN_REG][31:0];
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reg_i[DMA_WRITE_DESC_CONTROL_REG][1] = dma_s_axis_write_desc_ready;
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dma_s_axis_read_desc_valid = reg_o[DMA_READ_DESC_CONTROL_REG][0];
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dma_s_axis_read_desc_addr = reg_o[DMA_READ_DESC_ADDR_REG][31:0];
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dma_s_axis_read_desc_len = reg_o[DMA_READ_DESC_LEN_REG][31:0];
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reg_i[DMA_READ_DESC_CONTROL_REG][1] = dma_s_axis_read_desc_ready;
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end
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axi4_flat_to_if #(
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.ADDR_W (AXI_ADDR_WIDTH),
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.DATA_W (AXI_DATA_WIDTH)
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) i_axi4_flat_to_if (
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.s_axi_awid (dma_m_axi_awid),
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.s_axi_awaddr (dma_m_axi_awaddr),
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.s_axi_awlen (dma_m_axi_awlen),
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.s_axi_awsize (dma_m_axi_awsize),
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.s_axi_awburst (dma_m_axi_awburst),
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.s_axi_awlock (dma_m_axi_awlock),
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.s_axi_awcache (dma_m_axi_awcache),
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.s_axi_awprot (dma_m_axi_awprot),
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.s_axi_awqos (dma_m_axi_awqos),
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.s_axi_awregion (dma_m_axi_awregion),
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.s_axi_awuser (dma_m_axi_awuser),
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.s_axi_awvalid (dma_m_axi_awvalid),
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.s_axi_awready (dma_m_axi_awready),
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.s_axi_wdata (dma_m_axi_wdata),
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.s_axi_wstrb (dma_m_axi_wstrb),
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.s_axi_wlast (dma_m_axi_wlast),
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.s_axi_wuser (dma_m_axi_wuser),
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.s_axi_wvalid (dma_m_axi_wvalid),
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.s_axi_wready (dma_m_axi_wready),
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.s_axi_bid (dma_m_axi_bid),
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.s_axi_bresp (dma_m_axi_bresp),
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.s_axi_buser (dma_m_axi_buser),
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.s_axi_bvalid (dma_m_axi_bvalid),
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.s_axi_bready (dma_m_axi_bready),
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.s_axi_arid (dma_m_axi_arid),
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.s_axi_araddr (dma_m_axi_araddr),
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.s_axi_arlen (dma_m_axi_arlen),
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.s_axi_arsize (dma_m_axi_arsize),
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.s_axi_arburst (dma_m_axi_arburst),
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.s_axi_arlock (dma_m_axi_arlock),
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.s_axi_arcache (dma_m_axi_arcache),
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.s_axi_arprot (dma_m_axi_arprot),
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.s_axi_arqos (dma_m_axi_arqos),
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.s_axi_arregion (dma_m_axi_arregion),
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.s_axi_aruser (dma_m_axi_aruser),
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.s_axi_arvalid (dma_m_axi_arvalid),
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.s_axi_arready (dma_m_axi_arready),
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.s_axi_rid (dma_m_axi_rid),
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.s_axi_rdata (dma_m_axi_rdata),
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.s_axi_rresp (dma_m_axi_rresp),
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.s_axi_rlast (dma_m_axi_rlast),
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.s_axi_ruser (dma_m_axi_ruser),
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.s_axi_rvalid (dma_m_axi_rvalid),
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.s_axi_rready (dma_m_axi_rready),
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.m_axi (m_axi_data)
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);
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axi_dma #(
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.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
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.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
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.AXI_ID_WIDTH (AXI_ID_WIDTH),
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.AXI_MAX_BURST_LEN (AXI_MAX_BURST_LEN),
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.AXIS_LAST_ENABLE (AXIS_LAST_ENABLE),
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.AXIS_ID_ENABLE (AXIS_ID_ENABLE),
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.AXIS_ID_WIDTH (AXIS_ID_WIDTH),
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.AXIS_DEST_ENABLE (AXIS_DEST_ENABLE),
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.AXIS_DEST_WIDTH (AXIS_DEST_WIDTH),
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.AXIS_USER_ENABLE (AXIS_USER_ENABLE),
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.AXIS_USER_WIDTH (AXIS_USER_WIDTH),
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.LEN_WIDTH (LEN_WIDTH),
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.TAG_WIDTH (TAG_WIDTH),
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.ENABLE_SG (ENABLE_SG),
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.ENABLE_UNALIGNED (ENABLE_UNALIGNED)
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) i_axi_dma (
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.clk (dma_clk),
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.rst (dma_rst),
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.s_axis_read_desc_addr (dma_s_axis_read_desc_addr),
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.s_axis_read_desc_len (dma_s_axis_read_desc_len),
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.s_axis_read_desc_tag (dma_s_axis_read_desc_tag),
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.s_axis_read_desc_id (dma_s_axis_read_desc_id),
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.s_axis_read_desc_dest (dma_s_axis_read_desc_dest),
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.s_axis_read_desc_user (dma_s_axis_read_desc_user),
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.s_axis_read_desc_valid (dma_s_axis_read_desc_valid),
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.s_axis_read_desc_ready (dma_s_axis_read_desc_ready),
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.m_axis_read_desc_status_tag (dma_m_axis_read_desc_status_tag),
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.m_axis_read_desc_status_error (dma_m_axis_read_desc_status_error),
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.m_axis_read_desc_status_valid (dma_m_axis_read_desc_status_valid),
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.m_axis_read_data_tdata (m_axis_read_data_tdata),
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.m_axis_read_data_tkeep (m_axis_read_data_tkeep),
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.m_axis_read_data_tvalid (m_axis_read_data_tvalid),
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.m_axis_read_data_tready (m_axis_read_data_tready),
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.m_axis_read_data_tlast (m_axis_read_data_tlast),
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.m_axis_read_data_tid (m_axis_read_data_tid),
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.m_axis_read_data_tdest (m_axis_read_data_tdest),
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.m_axis_read_data_tuser (m_axis_read_data_tuser),
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.s_axis_write_desc_addr (dma_s_axis_write_desc_addr),
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.s_axis_write_desc_len (dma_s_axis_write_desc_len),
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.s_axis_write_desc_tag (dma_s_axis_write_desc_tag),
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.s_axis_write_desc_valid (dma_s_axis_write_desc_valid),
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.s_axis_write_desc_ready (dma_s_axis_write_desc_ready),
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.m_axis_write_desc_status_len (dma_m_axis_write_desc_status_len),
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.m_axis_write_desc_status_tag (dma_m_axis_write_desc_status_tag),
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.m_axis_write_desc_status_id (dma_m_axis_write_desc_status_id),
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.m_axis_write_desc_status_dest (dma_m_axis_write_desc_status_dest),
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.m_axis_write_desc_status_user (dma_m_axis_write_desc_status_user),
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.m_axis_write_desc_status_error (dma_m_axis_write_desc_status_error),
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.m_axis_write_desc_status_valid (dma_m_axis_write_desc_status_valid),
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.s_axis_write_data_tdata (s_axis_write_data_tdata),
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.s_axis_write_data_tkeep (s_axis_write_data_tkeep),
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.s_axis_write_data_tvalid (s_axis_write_data_tvalid),
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.s_axis_write_data_tready (s_axis_write_data_tready),
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.s_axis_write_data_tlast (s_axis_write_data_tlast),
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.s_axis_write_data_tid (s_axis_write_data_tid),
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.s_axis_write_data_tdest (s_axis_write_data_tdest),
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.s_axis_write_data_tuser (s_axis_write_data_tuser),
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.m_axi_awid (dma_m_axi_awid),
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.m_axi_awaddr (dma_m_axi_awaddr),
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.m_axi_awlen (dma_m_axi_awlen),
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.m_axi_awsize (dma_m_axi_awsize),
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.m_axi_awburst (dma_m_axi_awburst),
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.m_axi_awlock (dma_m_axi_awlock),
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.m_axi_awcache (dma_m_axi_awcache),
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.m_axi_awprot (dma_m_axi_awprot),
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.m_axi_awvalid (dma_m_axi_awvalid),
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.m_axi_awready (dma_m_axi_awready),
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.m_axi_wdata (dma_m_axi_wdata),
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.m_axi_wstrb (dma_m_axi_wstrb),
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.m_axi_wlast (dma_m_axi_wlast),
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.m_axi_wvalid (dma_m_axi_wvalid),
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.m_axi_wready (dma_m_axi_wready),
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.m_axi_bid (dma_m_axi_bid),
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.m_axi_bresp (dma_m_axi_bresp),
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.m_axi_bvalid (dma_m_axi_bvalid),
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.m_axi_bready (dma_m_axi_bready),
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.m_axi_arid (dma_m_axi_arid),
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.m_axi_araddr (dma_m_axi_araddr),
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.m_axi_arlen (dma_m_axi_arlen),
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.m_axi_arsize (dma_m_axi_arsize),
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.m_axi_arburst (dma_m_axi_arburst),
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.m_axi_arlock (dma_m_axi_arlock),
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.m_axi_arcache (dma_m_axi_arcache),
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.m_axi_arprot (dma_m_axi_arprot),
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.m_axi_arvalid (dma_m_axi_arvalid),
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.m_axi_arready (dma_m_axi_arready),
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.m_axi_rid (dma_m_axi_rid),
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.m_axi_rdata (dma_m_axi_rdata),
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.m_axi_rresp (dma_m_axi_rresp),
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.m_axi_rlast (dma_m_axi_rlast),
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.m_axi_rvalid (dma_m_axi_rvalid),
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.m_axi_rready (dma_m_axi_rready),
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.read_enable (dma_read_enable),
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.write_enable (dma_write_enable),
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.write_abort (dma_write_abort)
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);
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endmodule |