655 lines
31 KiB
Systemverilog
655 lines
31 KiB
Systemverilog
/*
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Copyright (c) 2020 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 3x3 crossbar (wrapper)
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*/
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module axi_crossbar_core_wrapper #
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(
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// Width of data bus in bits
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parameter DATA_WIDTH = 32,
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// Width of address bus in bits
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parameter ADDR_WIDTH = 32,
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// Width of wstrb (width of data bus in words)
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parameter STRB_WIDTH = (DATA_WIDTH/8),
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// Input ID field width (from AXI masters)
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parameter S_ID_WIDTH = 8,
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// Output ID field width (towards AXI slaves)
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// Additional bits required for response routing
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parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT),
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// Propagate awuser signal
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parameter AWUSER_ENABLE = 0,
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// Width of awuser signal
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parameter AWUSER_WIDTH = 1,
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// Propagate wuser signal
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parameter WUSER_ENABLE = 0,
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// Width of wuser signal
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parameter WUSER_WIDTH = 1,
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// Propagate buser signal
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parameter BUSER_ENABLE = 0,
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// Width of buser signal
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parameter BUSER_WIDTH = 1,
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// Propagate aruser signal
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parameter ARUSER_ENABLE = 0,
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// Width of aruser signal
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parameter ARUSER_WIDTH = 1,
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// Propagate ruser signal
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parameter RUSER_ENABLE = 0,
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// Width of ruser signal
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parameter RUSER_WIDTH = 1,
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// Number of concurrent unique IDs
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parameter S00_THREADS = 2,
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// Number of concurrent operations
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parameter S00_ACCEPT = 16,
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// Number of concurrent unique IDs
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parameter S01_THREADS = 2,
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// Number of concurrent operations
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parameter S01_ACCEPT = 16,
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// Number of concurrent unique IDs
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parameter S02_THREADS = 2,
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// Number of concurrent operations
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parameter S02_ACCEPT = 16,
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// Number of regions per master interface
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parameter M_REGIONS = 1,
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// Master interface base addresses
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// M_REGIONS concatenated fields of ADDR_WIDTH bits
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parameter M00_BASE_ADDR = 0,
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// Master interface address widths
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// M_REGIONS concatenated fields of 32 bits
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parameter M00_ADDR_WIDTH = {M_REGIONS{32'd24}},
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// Read connections between interfaces
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// S_COUNT bits
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parameter M00_CONNECT_READ = 3'b111,
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// Write connections between interfaces
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// S_COUNT bits
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parameter M00_CONNECT_WRITE = 3'b111,
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// Number of concurrent operations for each master interface
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parameter M00_ISSUE = 4,
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// Secure master (fail operations based on awprot/arprot)
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parameter M00_SECURE = 0,
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// Master interface base addresses
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// M_REGIONS concatenated fields of ADDR_WIDTH bits
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parameter M01_BASE_ADDR = 0,
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// Master interface address widths
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// M_REGIONS concatenated fields of 32 bits
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parameter M01_ADDR_WIDTH = {M_REGIONS{32'd24}},
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// Read connections between interfaces
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// S_COUNT bits
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parameter M01_CONNECT_READ = 3'b111,
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// Write connections between interfaces
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// S_COUNT bits
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parameter M01_CONNECT_WRITE = 3'b111,
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// Number of concurrent operations for each master interface
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parameter M01_ISSUE = 4,
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// Secure master (fail operations based on awprot/arprot)
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parameter M01_SECURE = 0,
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// Master interface base addresses
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// M_REGIONS concatenated fields of ADDR_WIDTH bits
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parameter M02_BASE_ADDR = 0,
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// Master interface address widths
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// M_REGIONS concatenated fields of 32 bits
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parameter M02_ADDR_WIDTH = {M_REGIONS{32'd24}},
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// Read connections between interfaces
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// S_COUNT bits
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parameter M02_CONNECT_READ = 3'b111,
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// Write connections between interfaces
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// S_COUNT bits
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parameter M02_CONNECT_WRITE = 3'b111,
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// Number of concurrent operations for each master interface
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parameter M02_ISSUE = 4,
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// Secure master (fail operations based on awprot/arprot)
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parameter M02_SECURE = 0,
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// Slave interface AW channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S00_AW_REG_TYPE = 0,
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// Slave interface W channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S00_W_REG_TYPE = 0,
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// Slave interface B channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S00_B_REG_TYPE = 1,
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// Slave interface AR channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S00_AR_REG_TYPE = 0,
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// Slave interface R channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S00_R_REG_TYPE = 2,
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// Slave interface AW channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S01_AW_REG_TYPE = 0,
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// Slave interface W channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S01_W_REG_TYPE = 0,
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// Slave interface B channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S01_B_REG_TYPE = 1,
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// Slave interface AR channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S01_AR_REG_TYPE = 0,
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// Slave interface R channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S01_R_REG_TYPE = 2,
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// Slave interface AW channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S02_AW_REG_TYPE = 0,
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// Slave interface W channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S02_W_REG_TYPE = 0,
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// Slave interface B channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S02_B_REG_TYPE = 1,
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// Slave interface AR channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S02_AR_REG_TYPE = 0,
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// Slave interface R channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S02_R_REG_TYPE = 2,
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// Master interface AW channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M00_AW_REG_TYPE = 1,
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// Master interface W channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M00_W_REG_TYPE = 2,
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// Master interface B channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M00_B_REG_TYPE = 0,
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// Master interface AR channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M00_AR_REG_TYPE = 1,
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// Master interface R channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M00_R_REG_TYPE = 0,
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// Master interface AW channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M01_AW_REG_TYPE = 1,
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// Master interface W channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M01_W_REG_TYPE = 2,
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// Master interface B channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M01_B_REG_TYPE = 0,
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// Master interface AR channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M01_AR_REG_TYPE = 1,
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// Master interface R channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M01_R_REG_TYPE = 0,
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// Master interface AW channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M02_AW_REG_TYPE = 1,
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// Master interface W channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M02_W_REG_TYPE = 2,
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// Master interface B channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M02_B_REG_TYPE = 0,
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// Master interface AR channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M02_AR_REG_TYPE = 1,
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// Master interface R channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M02_R_REG_TYPE = 0
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI slave interface
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*/
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input wire [S_ID_WIDTH-1:0] s00_axi_awid,
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input wire [ADDR_WIDTH-1:0] s00_axi_awaddr,
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input wire [7:0] s00_axi_awlen,
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input wire [2:0] s00_axi_awsize,
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input wire [1:0] s00_axi_awburst,
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input wire s00_axi_awlock,
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input wire [3:0] s00_axi_awcache,
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input wire [2:0] s00_axi_awprot,
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input wire [3:0] s00_axi_awqos,
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input wire [AWUSER_WIDTH-1:0] s00_axi_awuser,
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input wire s00_axi_awvalid,
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output wire s00_axi_awready,
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input wire [DATA_WIDTH-1:0] s00_axi_wdata,
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input wire [STRB_WIDTH-1:0] s00_axi_wstrb,
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input wire s00_axi_wlast,
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input wire [WUSER_WIDTH-1:0] s00_axi_wuser,
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input wire s00_axi_wvalid,
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output wire s00_axi_wready,
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output wire [S_ID_WIDTH-1:0] s00_axi_bid,
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output wire [1:0] s00_axi_bresp,
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output wire [BUSER_WIDTH-1:0] s00_axi_buser,
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output wire s00_axi_bvalid,
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input wire s00_axi_bready,
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input wire [S_ID_WIDTH-1:0] s00_axi_arid,
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input wire [ADDR_WIDTH-1:0] s00_axi_araddr,
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input wire [7:0] s00_axi_arlen,
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input wire [2:0] s00_axi_arsize,
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input wire [1:0] s00_axi_arburst,
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input wire s00_axi_arlock,
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input wire [3:0] s00_axi_arcache,
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input wire [2:0] s00_axi_arprot,
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input wire [3:0] s00_axi_arqos,
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input wire [ARUSER_WIDTH-1:0] s00_axi_aruser,
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input wire s00_axi_arvalid,
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output wire s00_axi_arready,
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output wire [S_ID_WIDTH-1:0] s00_axi_rid,
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output wire [DATA_WIDTH-1:0] s00_axi_rdata,
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output wire [1:0] s00_axi_rresp,
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output wire s00_axi_rlast,
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output wire [RUSER_WIDTH-1:0] s00_axi_ruser,
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output wire s00_axi_rvalid,
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input wire s00_axi_rready,
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input wire [S_ID_WIDTH-1:0] s01_axi_awid,
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input wire [ADDR_WIDTH-1:0] s01_axi_awaddr,
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input wire [7:0] s01_axi_awlen,
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input wire [2:0] s01_axi_awsize,
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input wire [1:0] s01_axi_awburst,
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input wire s01_axi_awlock,
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input wire [3:0] s01_axi_awcache,
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input wire [2:0] s01_axi_awprot,
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input wire [3:0] s01_axi_awqos,
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input wire [AWUSER_WIDTH-1:0] s01_axi_awuser,
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input wire s01_axi_awvalid,
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output wire s01_axi_awready,
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input wire [DATA_WIDTH-1:0] s01_axi_wdata,
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input wire [STRB_WIDTH-1:0] s01_axi_wstrb,
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input wire s01_axi_wlast,
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input wire [WUSER_WIDTH-1:0] s01_axi_wuser,
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input wire s01_axi_wvalid,
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output wire s01_axi_wready,
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output wire [S_ID_WIDTH-1:0] s01_axi_bid,
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output wire [1:0] s01_axi_bresp,
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output wire [BUSER_WIDTH-1:0] s01_axi_buser,
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output wire s01_axi_bvalid,
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input wire s01_axi_bready,
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input wire [S_ID_WIDTH-1:0] s01_axi_arid,
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input wire [ADDR_WIDTH-1:0] s01_axi_araddr,
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input wire [7:0] s01_axi_arlen,
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input wire [2:0] s01_axi_arsize,
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input wire [1:0] s01_axi_arburst,
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input wire s01_axi_arlock,
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input wire [3:0] s01_axi_arcache,
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input wire [2:0] s01_axi_arprot,
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input wire [3:0] s01_axi_arqos,
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input wire [ARUSER_WIDTH-1:0] s01_axi_aruser,
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input wire s01_axi_arvalid,
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output wire s01_axi_arready,
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output wire [S_ID_WIDTH-1:0] s01_axi_rid,
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output wire [DATA_WIDTH-1:0] s01_axi_rdata,
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output wire [1:0] s01_axi_rresp,
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output wire s01_axi_rlast,
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output wire [RUSER_WIDTH-1:0] s01_axi_ruser,
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output wire s01_axi_rvalid,
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input wire s01_axi_rready,
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input wire [S_ID_WIDTH-1:0] s02_axi_awid,
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input wire [ADDR_WIDTH-1:0] s02_axi_awaddr,
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input wire [7:0] s02_axi_awlen,
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input wire [2:0] s02_axi_awsize,
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input wire [1:0] s02_axi_awburst,
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input wire s02_axi_awlock,
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input wire [3:0] s02_axi_awcache,
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input wire [2:0] s02_axi_awprot,
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input wire [3:0] s02_axi_awqos,
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input wire [AWUSER_WIDTH-1:0] s02_axi_awuser,
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input wire s02_axi_awvalid,
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output wire s02_axi_awready,
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input wire [DATA_WIDTH-1:0] s02_axi_wdata,
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input wire [STRB_WIDTH-1:0] s02_axi_wstrb,
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input wire s02_axi_wlast,
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input wire [WUSER_WIDTH-1:0] s02_axi_wuser,
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input wire s02_axi_wvalid,
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output wire s02_axi_wready,
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output wire [S_ID_WIDTH-1:0] s02_axi_bid,
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output wire [1:0] s02_axi_bresp,
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output wire [BUSER_WIDTH-1:0] s02_axi_buser,
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output wire s02_axi_bvalid,
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input wire s02_axi_bready,
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input wire [S_ID_WIDTH-1:0] s02_axi_arid,
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input wire [ADDR_WIDTH-1:0] s02_axi_araddr,
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input wire [7:0] s02_axi_arlen,
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input wire [2:0] s02_axi_arsize,
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input wire [1:0] s02_axi_arburst,
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input wire s02_axi_arlock,
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input wire [3:0] s02_axi_arcache,
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input wire [2:0] s02_axi_arprot,
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input wire [3:0] s02_axi_arqos,
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input wire [ARUSER_WIDTH-1:0] s02_axi_aruser,
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input wire s02_axi_arvalid,
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output wire s02_axi_arready,
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output wire [S_ID_WIDTH-1:0] s02_axi_rid,
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output wire [DATA_WIDTH-1:0] s02_axi_rdata,
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output wire [1:0] s02_axi_rresp,
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output wire s02_axi_rlast,
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output wire [RUSER_WIDTH-1:0] s02_axi_ruser,
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output wire s02_axi_rvalid,
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input wire s02_axi_rready,
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/*
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* AXI master interface
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*/
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output wire [M_ID_WIDTH-1:0] m00_axi_awid,
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output wire [ADDR_WIDTH-1:0] m00_axi_awaddr,
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output wire [7:0] m00_axi_awlen,
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output wire [2:0] m00_axi_awsize,
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output wire [1:0] m00_axi_awburst,
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output wire m00_axi_awlock,
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output wire [3:0] m00_axi_awcache,
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output wire [2:0] m00_axi_awprot,
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output wire [3:0] m00_axi_awqos,
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output wire [3:0] m00_axi_awregion,
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output wire [AWUSER_WIDTH-1:0] m00_axi_awuser,
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output wire m00_axi_awvalid,
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input wire m00_axi_awready,
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output wire [DATA_WIDTH-1:0] m00_axi_wdata,
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output wire [STRB_WIDTH-1:0] m00_axi_wstrb,
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output wire m00_axi_wlast,
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output wire [WUSER_WIDTH-1:0] m00_axi_wuser,
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output wire m00_axi_wvalid,
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input wire m00_axi_wready,
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input wire [M_ID_WIDTH-1:0] m00_axi_bid,
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input wire [1:0] m00_axi_bresp,
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input wire [BUSER_WIDTH-1:0] m00_axi_buser,
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input wire m00_axi_bvalid,
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output wire m00_axi_bready,
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output wire [M_ID_WIDTH-1:0] m00_axi_arid,
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output wire [ADDR_WIDTH-1:0] m00_axi_araddr,
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output wire [7:0] m00_axi_arlen,
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output wire [2:0] m00_axi_arsize,
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output wire [1:0] m00_axi_arburst,
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output wire m00_axi_arlock,
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output wire [3:0] m00_axi_arcache,
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output wire [2:0] m00_axi_arprot,
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output wire [3:0] m00_axi_arqos,
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output wire [3:0] m00_axi_arregion,
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output wire [ARUSER_WIDTH-1:0] m00_axi_aruser,
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output wire m00_axi_arvalid,
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input wire m00_axi_arready,
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input wire [M_ID_WIDTH-1:0] m00_axi_rid,
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input wire [DATA_WIDTH-1:0] m00_axi_rdata,
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input wire [1:0] m00_axi_rresp,
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input wire m00_axi_rlast,
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input wire [RUSER_WIDTH-1:0] m00_axi_ruser,
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input wire m00_axi_rvalid,
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output wire m00_axi_rready,
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output wire [M_ID_WIDTH-1:0] m01_axi_awid,
|
|
output wire [ADDR_WIDTH-1:0] m01_axi_awaddr,
|
|
output wire [7:0] m01_axi_awlen,
|
|
output wire [2:0] m01_axi_awsize,
|
|
output wire [1:0] m01_axi_awburst,
|
|
output wire m01_axi_awlock,
|
|
output wire [3:0] m01_axi_awcache,
|
|
output wire [2:0] m01_axi_awprot,
|
|
output wire [3:0] m01_axi_awqos,
|
|
output wire [3:0] m01_axi_awregion,
|
|
output wire [AWUSER_WIDTH-1:0] m01_axi_awuser,
|
|
output wire m01_axi_awvalid,
|
|
input wire m01_axi_awready,
|
|
output wire [DATA_WIDTH-1:0] m01_axi_wdata,
|
|
output wire [STRB_WIDTH-1:0] m01_axi_wstrb,
|
|
output wire m01_axi_wlast,
|
|
output wire [WUSER_WIDTH-1:0] m01_axi_wuser,
|
|
output wire m01_axi_wvalid,
|
|
input wire m01_axi_wready,
|
|
input wire [M_ID_WIDTH-1:0] m01_axi_bid,
|
|
input wire [1:0] m01_axi_bresp,
|
|
input wire [BUSER_WIDTH-1:0] m01_axi_buser,
|
|
input wire m01_axi_bvalid,
|
|
output wire m01_axi_bready,
|
|
output wire [M_ID_WIDTH-1:0] m01_axi_arid,
|
|
output wire [ADDR_WIDTH-1:0] m01_axi_araddr,
|
|
output wire [7:0] m01_axi_arlen,
|
|
output wire [2:0] m01_axi_arsize,
|
|
output wire [1:0] m01_axi_arburst,
|
|
output wire m01_axi_arlock,
|
|
output wire [3:0] m01_axi_arcache,
|
|
output wire [2:0] m01_axi_arprot,
|
|
output wire [3:0] m01_axi_arqos,
|
|
output wire [3:0] m01_axi_arregion,
|
|
output wire [ARUSER_WIDTH-1:0] m01_axi_aruser,
|
|
output wire m01_axi_arvalid,
|
|
input wire m01_axi_arready,
|
|
input wire [M_ID_WIDTH-1:0] m01_axi_rid,
|
|
input wire [DATA_WIDTH-1:0] m01_axi_rdata,
|
|
input wire [1:0] m01_axi_rresp,
|
|
input wire m01_axi_rlast,
|
|
input wire [RUSER_WIDTH-1:0] m01_axi_ruser,
|
|
input wire m01_axi_rvalid,
|
|
output wire m01_axi_rready,
|
|
|
|
output wire [M_ID_WIDTH-1:0] m02_axi_awid,
|
|
output wire [ADDR_WIDTH-1:0] m02_axi_awaddr,
|
|
output wire [7:0] m02_axi_awlen,
|
|
output wire [2:0] m02_axi_awsize,
|
|
output wire [1:0] m02_axi_awburst,
|
|
output wire m02_axi_awlock,
|
|
output wire [3:0] m02_axi_awcache,
|
|
output wire [2:0] m02_axi_awprot,
|
|
output wire [3:0] m02_axi_awqos,
|
|
output wire [3:0] m02_axi_awregion,
|
|
output wire [AWUSER_WIDTH-1:0] m02_axi_awuser,
|
|
output wire m02_axi_awvalid,
|
|
input wire m02_axi_awready,
|
|
output wire [DATA_WIDTH-1:0] m02_axi_wdata,
|
|
output wire [STRB_WIDTH-1:0] m02_axi_wstrb,
|
|
output wire m02_axi_wlast,
|
|
output wire [WUSER_WIDTH-1:0] m02_axi_wuser,
|
|
output wire m02_axi_wvalid,
|
|
input wire m02_axi_wready,
|
|
input wire [M_ID_WIDTH-1:0] m02_axi_bid,
|
|
input wire [1:0] m02_axi_bresp,
|
|
input wire [BUSER_WIDTH-1:0] m02_axi_buser,
|
|
input wire m02_axi_bvalid,
|
|
output wire m02_axi_bready,
|
|
output wire [M_ID_WIDTH-1:0] m02_axi_arid,
|
|
output wire [ADDR_WIDTH-1:0] m02_axi_araddr,
|
|
output wire [7:0] m02_axi_arlen,
|
|
output wire [2:0] m02_axi_arsize,
|
|
output wire [1:0] m02_axi_arburst,
|
|
output wire m02_axi_arlock,
|
|
output wire [3:0] m02_axi_arcache,
|
|
output wire [2:0] m02_axi_arprot,
|
|
output wire [3:0] m02_axi_arqos,
|
|
output wire [3:0] m02_axi_arregion,
|
|
output wire [ARUSER_WIDTH-1:0] m02_axi_aruser,
|
|
output wire m02_axi_arvalid,
|
|
input wire m02_axi_arready,
|
|
input wire [M_ID_WIDTH-1:0] m02_axi_rid,
|
|
input wire [DATA_WIDTH-1:0] m02_axi_rdata,
|
|
input wire [1:0] m02_axi_rresp,
|
|
input wire m02_axi_rlast,
|
|
input wire [RUSER_WIDTH-1:0] m02_axi_ruser,
|
|
input wire m02_axi_rvalid,
|
|
output wire m02_axi_rready
|
|
);
|
|
|
|
localparam S_COUNT = 3;
|
|
localparam M_COUNT = 3;
|
|
|
|
// parameter sizing helpers
|
|
function [ADDR_WIDTH*M_REGIONS-1:0] w_a_r(input [ADDR_WIDTH*M_REGIONS-1:0] val);
|
|
w_a_r = val;
|
|
endfunction
|
|
|
|
function [32*M_REGIONS-1:0] w_32_r(input [32*M_REGIONS-1:0] val);
|
|
w_32_r = val;
|
|
endfunction
|
|
|
|
function [S_COUNT-1:0] w_s(input [S_COUNT-1:0] val);
|
|
w_s = val;
|
|
endfunction
|
|
|
|
function [31:0] w_32(input [31:0] val);
|
|
w_32 = val;
|
|
endfunction
|
|
|
|
function [1:0] w_2(input [1:0] val);
|
|
w_2 = val;
|
|
endfunction
|
|
|
|
function w_1(input val);
|
|
w_1 = val;
|
|
endfunction
|
|
|
|
axi_crossbar #(
|
|
.S_COUNT(S_COUNT),
|
|
.M_COUNT(M_COUNT),
|
|
.DATA_WIDTH(DATA_WIDTH),
|
|
.ADDR_WIDTH(ADDR_WIDTH),
|
|
.STRB_WIDTH(STRB_WIDTH),
|
|
.S_ID_WIDTH(S_ID_WIDTH),
|
|
.M_ID_WIDTH(M_ID_WIDTH),
|
|
.AWUSER_ENABLE(AWUSER_ENABLE),
|
|
.AWUSER_WIDTH(AWUSER_WIDTH),
|
|
.WUSER_ENABLE(WUSER_ENABLE),
|
|
.WUSER_WIDTH(WUSER_WIDTH),
|
|
.BUSER_ENABLE(BUSER_ENABLE),
|
|
.BUSER_WIDTH(BUSER_WIDTH),
|
|
.ARUSER_ENABLE(ARUSER_ENABLE),
|
|
.ARUSER_WIDTH(ARUSER_WIDTH),
|
|
.RUSER_ENABLE(RUSER_ENABLE),
|
|
.RUSER_WIDTH(RUSER_WIDTH),
|
|
.S_THREADS({ w_32(S02_THREADS), w_32(S01_THREADS), w_32(S00_THREADS) }),
|
|
.S_ACCEPT({ w_32(S02_ACCEPT), w_32(S01_ACCEPT), w_32(S00_ACCEPT) }),
|
|
.M_REGIONS(M_REGIONS),
|
|
.M_BASE_ADDR({ w_a_r(M02_BASE_ADDR), w_a_r(M01_BASE_ADDR), w_a_r(M00_BASE_ADDR) }),
|
|
.M_ADDR_WIDTH({ w_32_r(M02_ADDR_WIDTH), w_32_r(M01_ADDR_WIDTH), w_32_r(M00_ADDR_WIDTH) }),
|
|
.M_CONNECT_READ({ w_s(M02_CONNECT_READ), w_s(M01_CONNECT_READ), w_s(M00_CONNECT_READ) }),
|
|
.M_CONNECT_WRITE({ w_s(M02_CONNECT_WRITE), w_s(M01_CONNECT_WRITE), w_s(M00_CONNECT_WRITE) }),
|
|
.M_ISSUE({ w_32(M02_ISSUE), w_32(M01_ISSUE), w_32(M00_ISSUE) }),
|
|
.M_SECURE({ w_1(M02_SECURE), w_1(M01_SECURE), w_1(M00_SECURE) }),
|
|
.S_AR_REG_TYPE({ w_2(S02_AR_REG_TYPE), w_2(S01_AR_REG_TYPE), w_2(S00_AR_REG_TYPE) }),
|
|
.S_R_REG_TYPE({ w_2(S02_R_REG_TYPE), w_2(S01_R_REG_TYPE), w_2(S00_R_REG_TYPE) }),
|
|
.S_AW_REG_TYPE({ w_2(S02_AW_REG_TYPE), w_2(S01_AW_REG_TYPE), w_2(S00_AW_REG_TYPE) }),
|
|
.S_W_REG_TYPE({ w_2(S02_W_REG_TYPE), w_2(S01_W_REG_TYPE), w_2(S00_W_REG_TYPE) }),
|
|
.S_B_REG_TYPE({ w_2(S02_B_REG_TYPE), w_2(S01_B_REG_TYPE), w_2(S00_B_REG_TYPE) }),
|
|
.M_AR_REG_TYPE({ w_2(M02_AR_REG_TYPE), w_2(M01_AR_REG_TYPE), w_2(M00_AR_REG_TYPE) }),
|
|
.M_R_REG_TYPE({ w_2(M02_R_REG_TYPE), w_2(M01_R_REG_TYPE), w_2(M00_R_REG_TYPE) }),
|
|
.M_AW_REG_TYPE({ w_2(M02_AW_REG_TYPE), w_2(M01_AW_REG_TYPE), w_2(M00_AW_REG_TYPE) }),
|
|
.M_W_REG_TYPE({ w_2(M02_W_REG_TYPE), w_2(M01_W_REG_TYPE), w_2(M00_W_REG_TYPE) }),
|
|
.M_B_REG_TYPE({ w_2(M02_B_REG_TYPE), w_2(M01_B_REG_TYPE), w_2(M00_B_REG_TYPE) })
|
|
)
|
|
axi_crossbar_inst (
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.s_axi_awid({ s02_axi_awid, s01_axi_awid, s00_axi_awid }),
|
|
.s_axi_awaddr({ s02_axi_awaddr, s01_axi_awaddr, s00_axi_awaddr }),
|
|
.s_axi_awlen({ s02_axi_awlen, s01_axi_awlen, s00_axi_awlen }),
|
|
.s_axi_awsize({ s02_axi_awsize, s01_axi_awsize, s00_axi_awsize }),
|
|
.s_axi_awburst({ s02_axi_awburst, s01_axi_awburst, s00_axi_awburst }),
|
|
.s_axi_awlock({ s02_axi_awlock, s01_axi_awlock, s00_axi_awlock }),
|
|
.s_axi_awcache({ s02_axi_awcache, s01_axi_awcache, s00_axi_awcache }),
|
|
.s_axi_awprot({ s02_axi_awprot, s01_axi_awprot, s00_axi_awprot }),
|
|
.s_axi_awqos({ s02_axi_awqos, s01_axi_awqos, s00_axi_awqos }),
|
|
.s_axi_awuser({ s02_axi_awuser, s01_axi_awuser, s00_axi_awuser }),
|
|
.s_axi_awvalid({ s02_axi_awvalid, s01_axi_awvalid, s00_axi_awvalid }),
|
|
.s_axi_awready({ s02_axi_awready, s01_axi_awready, s00_axi_awready }),
|
|
.s_axi_wdata({ s02_axi_wdata, s01_axi_wdata, s00_axi_wdata }),
|
|
.s_axi_wstrb({ s02_axi_wstrb, s01_axi_wstrb, s00_axi_wstrb }),
|
|
.s_axi_wlast({ s02_axi_wlast, s01_axi_wlast, s00_axi_wlast }),
|
|
.s_axi_wuser({ s02_axi_wuser, s01_axi_wuser, s00_axi_wuser }),
|
|
.s_axi_wvalid({ s02_axi_wvalid, s01_axi_wvalid, s00_axi_wvalid }),
|
|
.s_axi_wready({ s02_axi_wready, s01_axi_wready, s00_axi_wready }),
|
|
.s_axi_bid({ s02_axi_bid, s01_axi_bid, s00_axi_bid }),
|
|
.s_axi_bresp({ s02_axi_bresp, s01_axi_bresp, s00_axi_bresp }),
|
|
.s_axi_buser({ s02_axi_buser, s01_axi_buser, s00_axi_buser }),
|
|
.s_axi_bvalid({ s02_axi_bvalid, s01_axi_bvalid, s00_axi_bvalid }),
|
|
.s_axi_bready({ s02_axi_bready, s01_axi_bready, s00_axi_bready }),
|
|
.s_axi_arid({ s02_axi_arid, s01_axi_arid, s00_axi_arid }),
|
|
.s_axi_araddr({ s02_axi_araddr, s01_axi_araddr, s00_axi_araddr }),
|
|
.s_axi_arlen({ s02_axi_arlen, s01_axi_arlen, s00_axi_arlen }),
|
|
.s_axi_arsize({ s02_axi_arsize, s01_axi_arsize, s00_axi_arsize }),
|
|
.s_axi_arburst({ s02_axi_arburst, s01_axi_arburst, s00_axi_arburst }),
|
|
.s_axi_arlock({ s02_axi_arlock, s01_axi_arlock, s00_axi_arlock }),
|
|
.s_axi_arcache({ s02_axi_arcache, s01_axi_arcache, s00_axi_arcache }),
|
|
.s_axi_arprot({ s02_axi_arprot, s01_axi_arprot, s00_axi_arprot }),
|
|
.s_axi_arqos({ s02_axi_arqos, s01_axi_arqos, s00_axi_arqos }),
|
|
.s_axi_aruser({ s02_axi_aruser, s01_axi_aruser, s00_axi_aruser }),
|
|
.s_axi_arvalid({ s02_axi_arvalid, s01_axi_arvalid, s00_axi_arvalid }),
|
|
.s_axi_arready({ s02_axi_arready, s01_axi_arready, s00_axi_arready }),
|
|
.s_axi_rid({ s02_axi_rid, s01_axi_rid, s00_axi_rid }),
|
|
.s_axi_rdata({ s02_axi_rdata, s01_axi_rdata, s00_axi_rdata }),
|
|
.s_axi_rresp({ s02_axi_rresp, s01_axi_rresp, s00_axi_rresp }),
|
|
.s_axi_rlast({ s02_axi_rlast, s01_axi_rlast, s00_axi_rlast }),
|
|
.s_axi_ruser({ s02_axi_ruser, s01_axi_ruser, s00_axi_ruser }),
|
|
.s_axi_rvalid({ s02_axi_rvalid, s01_axi_rvalid, s00_axi_rvalid }),
|
|
.s_axi_rready({ s02_axi_rready, s01_axi_rready, s00_axi_rready }),
|
|
.m_axi_awid({ m02_axi_awid, m01_axi_awid, m00_axi_awid }),
|
|
.m_axi_awaddr({ m02_axi_awaddr, m01_axi_awaddr, m00_axi_awaddr }),
|
|
.m_axi_awlen({ m02_axi_awlen, m01_axi_awlen, m00_axi_awlen }),
|
|
.m_axi_awsize({ m02_axi_awsize, m01_axi_awsize, m00_axi_awsize }),
|
|
.m_axi_awburst({ m02_axi_awburst, m01_axi_awburst, m00_axi_awburst }),
|
|
.m_axi_awlock({ m02_axi_awlock, m01_axi_awlock, m00_axi_awlock }),
|
|
.m_axi_awcache({ m02_axi_awcache, m01_axi_awcache, m00_axi_awcache }),
|
|
.m_axi_awprot({ m02_axi_awprot, m01_axi_awprot, m00_axi_awprot }),
|
|
.m_axi_awqos({ m02_axi_awqos, m01_axi_awqos, m00_axi_awqos }),
|
|
.m_axi_awregion({ m02_axi_awregion, m01_axi_awregion, m00_axi_awregion }),
|
|
.m_axi_awuser({ m02_axi_awuser, m01_axi_awuser, m00_axi_awuser }),
|
|
.m_axi_awvalid({ m02_axi_awvalid, m01_axi_awvalid, m00_axi_awvalid }),
|
|
.m_axi_awready({ m02_axi_awready, m01_axi_awready, m00_axi_awready }),
|
|
.m_axi_wdata({ m02_axi_wdata, m01_axi_wdata, m00_axi_wdata }),
|
|
.m_axi_wstrb({ m02_axi_wstrb, m01_axi_wstrb, m00_axi_wstrb }),
|
|
.m_axi_wlast({ m02_axi_wlast, m01_axi_wlast, m00_axi_wlast }),
|
|
.m_axi_wuser({ m02_axi_wuser, m01_axi_wuser, m00_axi_wuser }),
|
|
.m_axi_wvalid({ m02_axi_wvalid, m01_axi_wvalid, m00_axi_wvalid }),
|
|
.m_axi_wready({ m02_axi_wready, m01_axi_wready, m00_axi_wready }),
|
|
.m_axi_bid({ m02_axi_bid, m01_axi_bid, m00_axi_bid }),
|
|
.m_axi_bresp({ m02_axi_bresp, m01_axi_bresp, m00_axi_bresp }),
|
|
.m_axi_buser({ m02_axi_buser, m01_axi_buser, m00_axi_buser }),
|
|
.m_axi_bvalid({ m02_axi_bvalid, m01_axi_bvalid, m00_axi_bvalid }),
|
|
.m_axi_bready({ m02_axi_bready, m01_axi_bready, m00_axi_bready }),
|
|
.m_axi_arid({ m02_axi_arid, m01_axi_arid, m00_axi_arid }),
|
|
.m_axi_araddr({ m02_axi_araddr, m01_axi_araddr, m00_axi_araddr }),
|
|
.m_axi_arlen({ m02_axi_arlen, m01_axi_arlen, m00_axi_arlen }),
|
|
.m_axi_arsize({ m02_axi_arsize, m01_axi_arsize, m00_axi_arsize }),
|
|
.m_axi_arburst({ m02_axi_arburst, m01_axi_arburst, m00_axi_arburst }),
|
|
.m_axi_arlock({ m02_axi_arlock, m01_axi_arlock, m00_axi_arlock }),
|
|
.m_axi_arcache({ m02_axi_arcache, m01_axi_arcache, m00_axi_arcache }),
|
|
.m_axi_arprot({ m02_axi_arprot, m01_axi_arprot, m00_axi_arprot }),
|
|
.m_axi_arqos({ m02_axi_arqos, m01_axi_arqos, m00_axi_arqos }),
|
|
.m_axi_arregion({ m02_axi_arregion, m01_axi_arregion, m00_axi_arregion }),
|
|
.m_axi_aruser({ m02_axi_aruser, m01_axi_aruser, m00_axi_aruser }),
|
|
.m_axi_arvalid({ m02_axi_arvalid, m01_axi_arvalid, m00_axi_arvalid }),
|
|
.m_axi_arready({ m02_axi_arready, m01_axi_arready, m00_axi_arready }),
|
|
.m_axi_rid({ m02_axi_rid, m01_axi_rid, m00_axi_rid }),
|
|
.m_axi_rdata({ m02_axi_rdata, m01_axi_rdata, m00_axi_rdata }),
|
|
.m_axi_rresp({ m02_axi_rresp, m01_axi_rresp, m00_axi_rresp }),
|
|
.m_axi_rlast({ m02_axi_rlast, m01_axi_rlast, m00_axi_rlast }),
|
|
.m_axi_ruser({ m02_axi_ruser, m01_axi_ruser, m00_axi_ruser }),
|
|
.m_axi_rvalid({ m02_axi_rvalid, m01_axi_rvalid, m00_axi_rvalid }),
|
|
.m_axi_rready({ m02_axi_rready, m01_axi_rready, m00_axi_rready })
|
|
);
|
|
|
|
endmodule
|
|
|
|
`resetall
|