60 lines
2.5 KiB
Systemverilog
60 lines
2.5 KiB
Systemverilog
module axi4l_to_axi4 #(
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parameter int unsigned ADDR_W = 32,
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parameter int unsigned DATA_W = 32,
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parameter int unsigned ID_W = 4,
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parameter int unsigned USER_W = 1,
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parameter logic [ID_W-1:0] AXI_ID_CONST = '0,
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parameter logic [3:0] AXI_CACHE_CONST = 4'b0000,
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parameter logic [3:0] AXI_QOS_CONST = 4'b0000,
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parameter logic [3:0] AXI_REGION_CONST = 4'b0000
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)(
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axi4l_if.slave s_axil,
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axi4_if.master m_axi
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);
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assign m_axi.req.aw.id = AXI_ID_CONST;
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assign m_axi.req.aw.addr = s_axil.req.aw.addr;
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assign m_axi.req.aw.len = 8'd0;
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assign m_axi.req.aw.size = axi_pkg::axi_size_from_bytes(DATA_W/8);
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assign m_axi.req.aw.burst = axi_pkg::AXI_BURST_INCR;
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assign m_axi.req.aw.lock = 1'b0;
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assign m_axi.req.aw.cache = AXI_CACHE_CONST;
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assign m_axi.req.aw.prot = s_axil.req.aw.prot;
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assign m_axi.req.aw.qos = AXI_QOS_CONST;
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assign m_axi.req.aw.region = AXI_REGION_CONST;
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assign m_axi.req.aw.user = s_axil.req.aw.user;
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assign m_axi.req.aw.valid = s_axil.req.aw.valid;
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assign s_axil.resp.aw_ready = m_axi.resp.aw_ready;
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assign m_axi.req.w.data = s_axil.req.w.data;
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assign m_axi.req.w.strb = s_axil.req.w.strb;
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assign m_axi.req.w.last = 1'b1;
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assign m_axi.req.w.user = s_axil.req.w.user;
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assign m_axi.req.w.valid = s_axil.req.w.valid;
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assign s_axil.resp.w_ready = m_axi.resp.w_ready;
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assign s_axil.resp.b.resp = m_axi.resp.b.resp;
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assign s_axil.resp.b.user = m_axi.resp.b.user;
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assign s_axil.resp.b.valid = m_axi.resp.b.valid;
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assign m_axi.req.b_ready = s_axil.req.b_ready;
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assign m_axi.req.ar.id = AXI_ID_CONST;
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assign m_axi.req.ar.addr = s_axil.req.ar.addr;
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assign m_axi.req.ar.len = 8'd0;
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assign m_axi.req.ar.size = axi_pkg::axi_size_from_bytes(DATA_W/8);
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assign m_axi.req.ar.burst = axi_pkg::AXI_BURST_INCR;
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assign m_axi.req.ar.lock = 1'b0;
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assign m_axi.req.ar.cache = AXI_CACHE_CONST;
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assign m_axi.req.ar.prot = s_axil.req.ar.prot;
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assign m_axi.req.ar.qos = AXI_QOS_CONST;
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assign m_axi.req.ar.region = AXI_REGION_CONST;
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assign m_axi.req.ar.user = s_axil.req.ar.user;
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assign m_axi.req.ar.valid = s_axil.req.ar.valid;
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assign s_axil.resp.ar_ready = m_axi.resp.ar_ready;
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assign s_axil.resp.r.data = m_axi.resp.r.data;
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assign s_axil.resp.r.resp = m_axi.resp.r.resp;
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assign s_axil.resp.r.user = m_axi.resp.r.user;
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assign s_axil.resp.r.valid = m_axi.resp.r.valid;
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assign m_axi.req.r_ready = s_axil.req.r_ready;
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endmodule
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