57 lines
2.4 KiB
Systemverilog
57 lines
2.4 KiB
Systemverilog
module axi4l_if_to_flat #(
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parameter int unsigned ADDR_W = 32,
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parameter int unsigned DATA_W = 32,
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parameter int unsigned USER_W = 1
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)(
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axi4l_if.slave s_axil,
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output logic [ADDR_W-1:0] m_axil_awaddr,
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output logic [2:0] m_axil_awprot,
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output logic [USER_W-1:0] m_axil_awuser,
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output logic m_axil_awvalid,
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input logic m_axil_awready,
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output logic [DATA_W-1:0] m_axil_wdata,
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output logic [DATA_W/8-1:0] m_axil_wstrb,
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output logic [USER_W-1:0] m_axil_wuser,
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output logic m_axil_wvalid,
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input logic m_axil_wready,
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input logic [1:0] m_axil_bresp,
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input logic [USER_W-1:0] m_axil_buser,
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input logic m_axil_bvalid,
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output logic m_axil_bready,
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output logic [ADDR_W-1:0] m_axil_araddr,
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output logic [2:0] m_axil_arprot,
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output logic [USER_W-1:0] m_axil_aruser,
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output logic m_axil_arvalid,
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input logic m_axil_arready,
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input logic [DATA_W-1:0] m_axil_rdata,
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input logic [1:0] m_axil_rresp,
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input logic [USER_W-1:0] m_axil_ruser,
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input logic m_axil_rvalid,
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output logic m_axil_rready
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);
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assign m_axil_awaddr = s_axil.req.aw.addr;
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assign m_axil_awprot = s_axil.req.aw.prot;
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assign m_axil_awuser = s_axil.req.aw.user;
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assign m_axil_awvalid = s_axil.req.aw.valid;
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assign s_axil.resp.aw_ready = m_axil_awready;
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assign m_axil_wdata = s_axil.req.w.data;
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assign m_axil_wstrb = s_axil.req.w.strb;
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assign m_axil_wuser = s_axil.req.w.user;
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assign m_axil_wvalid = s_axil.req.w.valid;
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assign s_axil.resp.w_ready = m_axil_wready;
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assign s_axil.resp.b.resp = axi_pkg::axi_resp_t'(m_axil_bresp);
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assign s_axil.resp.b.user = m_axil_buser;
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assign s_axil.resp.b.valid = m_axil_bvalid;
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assign m_axil_bready = s_axil.req.b_ready;
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assign m_axil_araddr = s_axil.req.ar.addr;
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assign m_axil_arprot = s_axil.req.ar.prot;
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assign m_axil_aruser = s_axil.req.ar.user;
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assign m_axil_arvalid = s_axil.req.ar.valid;
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assign s_axil.resp.ar_ready = m_axil_arready;
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assign s_axil.resp.r.data = m_axil_rdata;
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assign s_axil.resp.r.resp = axi_pkg::axi_resp_t'(m_axil_rresp);
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assign s_axil.resp.r.user = m_axil_ruser;
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assign s_axil.resp.r.valid = m_axil_rvalid;
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assign m_axil_rready = s_axil.req.r_ready;
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endmodule
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