59 lines
2.4 KiB
Systemverilog
59 lines
2.4 KiB
Systemverilog
module axi4l_flat_to_if #(
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parameter int unsigned ADDR_W = 32,
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parameter int unsigned DATA_W = 32,
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parameter int unsigned USER_W = 1
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)(
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input logic aclk,
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input logic aresetn,
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input logic [ADDR_W-1:0] s_axil_awaddr,
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input logic [2:0] s_axil_awprot,
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input logic [USER_W-1:0] s_axil_awuser,
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input logic s_axil_awvalid,
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output logic s_axil_awready,
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input logic [DATA_W-1:0] s_axil_wdata,
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input logic [DATA_W/8-1:0] s_axil_wstrb,
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input logic [USER_W-1:0] s_axil_wuser,
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input logic s_axil_wvalid,
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output logic s_axil_wready,
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output logic [1:0] s_axil_bresp,
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output logic [USER_W-1:0] s_axil_buser,
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output logic s_axil_bvalid,
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input logic s_axil_bready,
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input logic [ADDR_W-1:0] s_axil_araddr,
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input logic [2:0] s_axil_arprot,
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input logic [USER_W-1:0] s_axil_aruser,
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input logic s_axil_arvalid,
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output logic s_axil_arready,
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output logic [DATA_W-1:0] s_axil_rdata,
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output logic [1:0] s_axil_rresp,
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output logic [USER_W-1:0] s_axil_ruser,
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output logic s_axil_rvalid,
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input logic s_axil_rready,
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axi4l_if.master m_axil
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);
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assign m_axil.req.aw.addr = s_axil_awaddr;
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assign m_axil.req.aw.prot = s_axil_awprot;
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assign m_axil.req.aw.user = s_axil_awuser;
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assign m_axil.req.aw.valid = s_axil_awvalid;
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assign s_axil_awready = m_axil.resp.aw_ready;
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assign m_axil.req.w.data = s_axil_wdata;
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assign m_axil.req.w.strb = s_axil_wstrb;
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assign m_axil.req.w.user = s_axil_wuser;
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assign m_axil.req.w.valid = s_axil_wvalid;
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assign s_axil_wready = m_axil.resp.w_ready;
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assign s_axil_bresp = m_axil.resp.b.resp;
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assign s_axil_buser = m_axil.resp.b.user;
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assign s_axil_bvalid = m_axil.resp.b.valid;
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assign m_axil.req.b_ready = s_axil_bready;
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assign m_axil.req.ar.addr = s_axil_araddr;
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assign m_axil.req.ar.prot = s_axil_arprot;
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assign m_axil.req.ar.user = s_axil_aruser;
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assign m_axil.req.ar.valid = s_axil_arvalid;
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assign s_axil_arready = m_axil.resp.ar_ready;
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assign s_axil_rdata = m_axil.resp.r.data;
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assign s_axil_rresp = m_axil.resp.r.resp;
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assign s_axil_ruser = m_axil.resp.r.user;
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assign s_axil_rvalid = m_axil.resp.r.valid;
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assign m_axil.req.r_ready = s_axil_rready;
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endmodule
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