98 lines
4.1 KiB
Systemverilog
98 lines
4.1 KiB
Systemverilog
module axi4_if_to_flat #(
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parameter int unsigned ADDR_W = 32,
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parameter int unsigned DATA_W = 64,
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parameter int unsigned ID_W = 4,
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parameter int unsigned USER_W = 1
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)(
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axi4_if.slave s_axi,
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output logic [ID_W-1:0] m_axi_awid,
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output logic [ADDR_W-1:0] m_axi_awaddr,
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output logic [7:0] m_axi_awlen,
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output logic [2:0] m_axi_awsize,
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output logic [1:0] m_axi_awburst,
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output logic m_axi_awlock,
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output logic [3:0] m_axi_awcache,
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output logic [2:0] m_axi_awprot,
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output logic [3:0] m_axi_awqos,
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output logic [3:0] m_axi_awregion,
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output logic [USER_W-1:0] m_axi_awuser,
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output logic m_axi_awvalid,
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input logic m_axi_awready,
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output logic [DATA_W-1:0] m_axi_wdata,
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output logic [DATA_W/8-1:0] m_axi_wstrb,
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output logic m_axi_wlast,
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output logic [USER_W-1:0] m_axi_wuser,
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output logic m_axi_wvalid,
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input logic m_axi_wready,
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input logic [ID_W-1:0] m_axi_bid,
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input logic [1:0] m_axi_bresp,
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input logic [USER_W-1:0] m_axi_buser,
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input logic m_axi_bvalid,
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output logic m_axi_bready,
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output logic [ID_W-1:0] m_axi_arid,
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output logic [ADDR_W-1:0] m_axi_araddr,
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output logic [7:0] m_axi_arlen,
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output logic [2:0] m_axi_arsize,
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output logic [1:0] m_axi_arburst,
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output logic m_axi_arlock,
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output logic [3:0] m_axi_arcache,
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output logic [2:0] m_axi_arprot,
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output logic [3:0] m_axi_arqos,
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output logic [3:0] m_axi_arregion,
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output logic [USER_W-1:0] m_axi_aruser,
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output logic m_axi_arvalid,
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input logic m_axi_arready,
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input logic [ID_W-1:0] m_axi_rid,
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input logic [DATA_W-1:0] m_axi_rdata,
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input logic [1:0] m_axi_rresp,
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input logic m_axi_rlast,
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input logic [USER_W-1:0] m_axi_ruser,
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input logic m_axi_rvalid,
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output logic m_axi_rready
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);
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assign m_axi_awid = s_axi.req.aw.id;
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assign m_axi_awaddr = s_axi.req.aw.addr;
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assign m_axi_awlen = s_axi.req.aw.len;
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assign m_axi_awsize = s_axi.req.aw.size;
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assign m_axi_awburst = s_axi.req.aw.burst;
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assign m_axi_awlock = s_axi.req.aw.lock;
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assign m_axi_awcache = s_axi.req.aw.cache;
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assign m_axi_awprot = s_axi.req.aw.prot;
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assign m_axi_awqos = s_axi.req.aw.qos;
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assign m_axi_awregion = s_axi.req.aw.region;
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assign m_axi_awuser = s_axi.req.aw.user;
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assign m_axi_awvalid = s_axi.req.aw.valid;
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assign s_axi.resp.aw_ready = m_axi_awready;
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assign m_axi_wdata = s_axi.req.w.data;
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assign m_axi_wstrb = s_axi.req.w.strb;
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assign m_axi_wlast = s_axi.req.w.last;
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assign m_axi_wuser = s_axi.req.w.user;
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assign m_axi_wvalid = s_axi.req.w.valid;
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assign s_axi.resp.w_ready = m_axi_wready;
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assign s_axi.resp.b.id = m_axi_bid;
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assign s_axi.resp.b.resp = axi_pkg::axi_resp_t'(m_axi_bresp);
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assign s_axi.resp.b.user = m_axi_buser;
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assign s_axi.resp.b.valid= m_axi_bvalid;
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assign m_axi_bready = s_axi.req.b_ready;
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assign m_axi_arid = s_axi.req.ar.id;
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assign m_axi_araddr = s_axi.req.ar.addr;
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assign m_axi_arlen = s_axi.req.ar.len;
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assign m_axi_arsize = s_axi.req.ar.size;
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assign m_axi_arburst = s_axi.req.ar.burst;
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assign m_axi_arlock = s_axi.req.ar.lock;
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assign m_axi_arcache = s_axi.req.ar.cache;
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assign m_axi_arprot = s_axi.req.ar.prot;
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assign m_axi_arqos = s_axi.req.ar.qos;
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assign m_axi_arregion = s_axi.req.ar.region;
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assign m_axi_aruser = s_axi.req.ar.user;
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assign m_axi_arvalid = s_axi.req.ar.valid;
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assign s_axi.resp.ar_ready = m_axi_arready;
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assign s_axi.resp.r.id = m_axi_rid;
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assign s_axi.resp.r.data = m_axi_rdata;
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assign s_axi.resp.r.resp = axi_pkg::axi_resp_t'(m_axi_rresp);
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assign s_axi.resp.r.last = m_axi_rlast;
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assign s_axi.resp.r.user = m_axi_ruser;
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assign s_axi.resp.r.valid= m_axi_rvalid;
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assign m_axi_rready = s_axi.req.r_ready;
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endmodule
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