98 lines
4.2 KiB
Systemverilog
98 lines
4.2 KiB
Systemverilog
module axi4_flat_to_if #(
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parameter int unsigned ADDR_W = 32,
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parameter int unsigned DATA_W = 64,
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parameter int unsigned ID_W = 4,
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parameter int unsigned USER_W = 1
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)(
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input logic [ID_W-1:0] s_axi_awid,
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input logic [ADDR_W-1:0] s_axi_awaddr,
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input logic [7:0] s_axi_awlen,
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input logic [2:0] s_axi_awsize,
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input logic [1:0] s_axi_awburst,
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input logic s_axi_awlock,
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input logic [3:0] s_axi_awcache,
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input logic [2:0] s_axi_awprot,
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input logic [3:0] s_axi_awqos,
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input logic [3:0] s_axi_awregion,
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input logic [USER_W-1:0] s_axi_awuser,
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input logic s_axi_awvalid,
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output logic s_axi_awready,
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input logic [DATA_W-1:0] s_axi_wdata,
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input logic [DATA_W/8-1:0] s_axi_wstrb,
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input logic s_axi_wlast,
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input logic [USER_W-1:0] s_axi_wuser,
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input logic s_axi_wvalid,
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output logic s_axi_wready,
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output logic [ID_W-1:0] s_axi_bid,
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output logic [1:0] s_axi_bresp,
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output logic [USER_W-1:0] s_axi_buser,
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output logic s_axi_bvalid,
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input logic s_axi_bready,
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input logic [ID_W-1:0] s_axi_arid,
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input logic [ADDR_W-1:0] s_axi_araddr,
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input logic [7:0] s_axi_arlen,
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input logic [2:0] s_axi_arsize,
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input logic [1:0] s_axi_arburst,
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input logic s_axi_arlock,
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input logic [3:0] s_axi_arcache,
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input logic [2:0] s_axi_arprot,
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input logic [3:0] s_axi_arqos,
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input logic [3:0] s_axi_arregion,
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input logic [USER_W-1:0] s_axi_aruser,
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input logic s_axi_arvalid,
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output logic s_axi_arready,
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output logic [ID_W-1:0] s_axi_rid,
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output logic [DATA_W-1:0] s_axi_rdata,
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output logic [1:0] s_axi_rresp,
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output logic s_axi_rlast,
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output logic [USER_W-1:0] s_axi_ruser,
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output logic s_axi_rvalid,
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input logic s_axi_rready,
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axi4_if.master m_axi
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);
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assign m_axi.req.aw.id = s_axi_awid;
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assign m_axi.req.aw.addr = s_axi_awaddr;
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assign m_axi.req.aw.len = s_axi_awlen;
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assign m_axi.req.aw.size = s_axi_awsize;
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assign m_axi.req.aw.burst = axi_pkg::axi_burst_t'(s_axi_awburst);
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assign m_axi.req.aw.lock = s_axi_awlock;
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assign m_axi.req.aw.cache = s_axi_awcache;
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assign m_axi.req.aw.prot = s_axi_awprot;
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assign m_axi.req.aw.qos = s_axi_awqos;
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assign m_axi.req.aw.region = s_axi_awregion;
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assign m_axi.req.aw.user = s_axi_awuser;
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assign m_axi.req.aw.valid = s_axi_awvalid;
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assign s_axi_awready = m_axi.resp.aw_ready;
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assign m_axi.req.w.data = s_axi_wdata;
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assign m_axi.req.w.strb = s_axi_wstrb;
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assign m_axi.req.w.last = s_axi_wlast;
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assign m_axi.req.w.user = s_axi_wuser;
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assign m_axi.req.w.valid = s_axi_wvalid;
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assign s_axi_wready = m_axi.resp.w_ready;
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assign s_axi_bid = m_axi.resp.b.id;
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assign s_axi_bresp = m_axi.resp.b.resp;
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assign s_axi_buser = m_axi.resp.b.user;
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assign s_axi_bvalid = m_axi.resp.b.valid;
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assign m_axi.req.b_ready = s_axi_bready;
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assign m_axi.req.ar.id = s_axi_arid;
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assign m_axi.req.ar.addr = s_axi_araddr;
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assign m_axi.req.ar.len = s_axi_arlen;
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assign m_axi.req.ar.size = s_axi_arsize;
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assign m_axi.req.ar.burst = axi_pkg::axi_burst_t'(s_axi_arburst);
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assign m_axi.req.ar.lock = s_axi_arlock;
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assign m_axi.req.ar.cache = s_axi_arcache;
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assign m_axi.req.ar.prot = s_axi_arprot;
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assign m_axi.req.ar.qos = s_axi_arqos;
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assign m_axi.req.ar.region = s_axi_arregion;
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assign m_axi.req.ar.user = s_axi_aruser;
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assign m_axi.req.ar.valid = s_axi_arvalid;
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assign s_axi_arready = m_axi.resp.ar_ready;
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assign s_axi_rid = m_axi.resp.r.id;
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assign s_axi_rdata = m_axi.resp.r.data;
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assign s_axi_rresp = m_axi.resp.r.resp;
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assign s_axi_rlast = m_axi.resp.r.last;
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assign s_axi_ruser = m_axi.resp.r.user;
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assign s_axi_rvalid = m_axi.resp.r.valid;
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assign m_axi.req.r_ready = s_axi_rready;
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endmodule
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