TOPLEVEL_LANG = verilog
SIM ?= verilator

PWD := $(shell pwd)
RTL_DIR ?= $(PWD)/../../rtl
TB_DIR  ?= $(PWD)

TOPLEVEL = tb_axis_loopback
MODULE   = test_axis_loopback

VERILOG_SOURCES += $(RTL_DIR)/axis_if.sv
VERILOG_SOURCES += $(RTL_DIR)/axis_flat_to_if.sv
VERILOG_SOURCES += $(RTL_DIR)/axis_if_to_flat.sv
VERILOG_SOURCES += $(RTL_DIR)/axis_desc_flat_to_if.sv
VERILOG_SOURCES += $(RTL_DIR)/axis_desc_if_to_flat.sv
VERILOG_SOURCES += $(TB_DIR)/axis_loopback.sv
VERILOG_SOURCES += $(TB_DIR)/tb_axis_loopback.sv

COMPILE_ARGS += -I$(RTL_DIR)
EXTRA_ARGS   += --trace
EXTRA_ARGS   += --trace-structs

include $(shell cocotb-config --makefiles)/Makefile.sim