TOPLEVEL_LANG = verilog
SIM ?= verilator

PWD := $(shell pwd)
PROJECT_ROOT ?= $(abspath $(PWD)/../../..)

AXI_IF_RTL_DIR       ?= $(PROJECT_ROOT)/axi/rtl
FORENCICH_AXI_RTL_DIR ?= $(PROJECT_ROOT)/external/verilog-axi/rtl
TB_DIR               ?= $(PWD)

TOPLEVEL = tb_axi_dma_wrapper
MODULE   = test_axi_dma_wrapper

export PYTHONPATH := $(TB_DIR):$(PYTHONPATH)

# Parameters for a quick make-based run. The pytest entrypoint can be used for
# wider parameter sweeps.
AXI_DATA_WIDTH    ?= 32
AXI_ADDR_WIDTH    ?= 16
AXI_ID_WIDTH      ?= 8
AXI_USER_WIDTH    ?= 1
AXI_MAX_BURST_LEN ?= 16
ENABLE_UNALIGNED  ?= 0

AXI_STRB_WIDTH    := $(shell expr $(AXI_DATA_WIDTH) / 8)
AXIS_DATA_WIDTH   ?= $(AXI_DATA_WIDTH)
AXIS_KEEP_WIDTH   := $(shell expr $(AXIS_DATA_WIDTH) / 8)
AXIS_KEEP_ENABLE  := $(shell [ $(AXIS_DATA_WIDTH) -gt 8 ] && echo 1 || echo 0)

VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axi_pkg.sv
VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axi_if.sv
VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axis_if.sv
VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axi4_flat_to_if.sv
VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axi4_if_to_flat.sv
VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axis_flat_to_if.sv
VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axis_if_to_flat.sv

VERILOG_SOURCES += $(FORENCICH_AXI_RTL_DIR)/axi_dma.v
VERILOG_SOURCES += $(FORENCICH_AXI_RTL_DIR)/axi_dma_rd.v
VERILOG_SOURCES += $(FORENCICH_AXI_RTL_DIR)/axi_dma_wr.v

VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axi_dma_if_wrapper.sv
VERILOG_SOURCES += $(TB_DIR)/tb_axi_dma_wrapper.sv

COMPILE_ARGS += -I$(AXI_IF_RTL_DIR)
COMPILE_ARGS += -I$(WRAPPER_RTL_DIR)
COMPILE_ARGS += -I$(FORENCICH_AXI_RTL_DIR)

# took this from forencich to silence 100+ warnings
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH -Wno-CASEINCOMPLETE

ifeq ($(SIM),verilator)
    EXTRA_ARGS += --trace
    EXTRA_ARGS += --trace-structs
    EXTRA_ARGS += -GAXI_DATA_WIDTH=$(AXI_DATA_WIDTH)
    EXTRA_ARGS += -GAXI_ADDR_WIDTH=$(AXI_ADDR_WIDTH)
    EXTRA_ARGS += -GAXI_STRB_WIDTH=$(AXI_STRB_WIDTH)
    EXTRA_ARGS += -GAXI_ID_WIDTH=$(AXI_ID_WIDTH)
    EXTRA_ARGS += -GAXI_USER_WIDTH=$(AXI_USER_WIDTH)
    EXTRA_ARGS += -GAXI_MAX_BURST_LEN=$(AXI_MAX_BURST_LEN)
    EXTRA_ARGS += -GAXIS_DATA_WIDTH=$(AXIS_DATA_WIDTH)
    EXTRA_ARGS += -GAXIS_KEEP_ENABLE=$(AXIS_KEEP_ENABLE)
    EXTRA_ARGS += -GAXIS_KEEP_WIDTH=$(AXIS_KEEP_WIDTH)
    EXTRA_ARGS += -GAXIS_LAST_ENABLE=1
    EXTRA_ARGS += -GAXIS_ID_ENABLE=1
    EXTRA_ARGS += -GAXIS_ID_WIDTH=8
    EXTRA_ARGS += -GAXIS_DEST_ENABLE=0
    EXTRA_ARGS += -GAXIS_DEST_WIDTH=8
    EXTRA_ARGS += -GAXIS_USER_ENABLE=1
    EXTRA_ARGS += -GAXIS_USER_WIDTH=1
    EXTRA_ARGS += -GLEN_WIDTH=20
    EXTRA_ARGS += -GTAG_WIDTH=8
    EXTRA_ARGS += -GENABLE_SG=0
    EXTRA_ARGS += -GENABLE_UNALIGNED=$(ENABLE_UNALIGNED)
endif

export PARAM_AXI_DATA_WIDTH=$(AXI_DATA_WIDTH)
export PARAM_ENABLE_UNALIGNED=$(ENABLE_UNALIGNED)

include $(shell cocotb-config --makefiles)/Makefile.sim