module axi4l_reg_map_example #(
  parameter int unsigned ADDR_W = 16,
  parameter int unsigned DATA_W = 32,
  parameter int unsigned USER_W = 1
)(
  input  logic clk,
  input  logic rst_n,
  axi4l_if.slave s_axil,

  output logic        start_o,
  output logic        soft_reset_o,
  output logic        enable_o,
  output logic        irq_enable_o,
  output logic [31:0] config_o,

  input  logic        busy_i,
  input  logic        done_i,
  input  logic        error_i,
  input  logic [7:0]  error_code_i
);
  import axi4l_reg_map_example_pkg::*;

  localparam int unsigned N_REGS = AXI4L_REG_MAP_EXAMPLE_N_REGS;

  logic [N_REGS-1:0][31:0] reg_i;
  logic [N_REGS-1:0][31:0] reg_o;
  logic [N_REGS-1:0][31:0] reg_pulse;

  axi4l_reg_map #(
    .ADDR_W   (ADDR_W),
    .DATA_W   (DATA_W),
    .USER_W   (USER_W),
    .N_REGS   (N_REGS),
    .REG_MODE (AXI4L_REG_MAP_EXAMPLE_REG_MODE),
    .REG_RST  (AXI4L_REG_MAP_EXAMPLE_REG_RST)
  ) u_reg_map (
    .clk       (clk),
    .rst_n     (rst_n),
    .s_axil    (s_axil),
    .reg_i     (reg_i),
    .reg_o     (reg_o),
    .reg_pulse (reg_pulse)
  );

  always_comb begin
    reg_i = '0;

    // REG_STATUS @ 0x04
    reg_i[REG_STATUS][STATUS_BUSY_BIT]  = busy_i;
    reg_i[REG_STATUS][STATUS_DONE_BIT]  = done_i;
    reg_i[REG_STATUS][STATUS_ERROR_BIT] = error_i;
    reg_i[REG_STATUS][STATUS_ERROR_CODE_MSB:STATUS_ERROR_CODE_LSB] = error_code_i;

    // REG_VERSION @ 0x0c
    reg_i[REG_VERSION] = VERSION_VAL;
  end

  // REG_CTRL @ 0x00
  assign start_o      = reg_pulse[REG_CTRL][CTRL_START_BIT];
  assign soft_reset_o = reg_pulse[REG_CTRL][CTRL_SOFT_RESET_BIT];
  assign enable_o     = reg_o[REG_CTRL][CTRL_ENABLE_BIT];
  assign irq_enable_o = reg_o[REG_CTRL][CTRL_IRQ_ENABLE_BIT];

  // REG_CONFIG @ 0x08
  assign config_o = reg_o[REG_CONFIG];

endmodule : axi4l_reg_map_example