package dma_axil_reg_map_pkg;

    localparam int unsigned DMA_AXIL_REG_MAP_N_REGS = 4;

    localparam logic [2:0] REG_BIT_RSVD = 3'd0;
    localparam logic [2:0] REG_BIT_RO   = 3'd1;
    localparam logic [2:0] REG_BIT_RW   = 3'd2;
    localparam logic [2:0] REG_BIT_W1S  = 3'd3;
    localparam logic [2:0] REG_BIT_W1C  = 3'd4;

    localparam DMA_WRITE_DESC_CONTROL_REG = 0;
    localparam DMA_WRITE_DESC_ADDR_REG = 1;
    localparam DMA_WRITE_DESC_LEN_REG = 2;
    localparam DMA_READ_DESC_CONTROL_REG = 3;
    localparam DMA_READ_DESC_ADDR_REG = 4;
    localparam DMA_READ_DESC_LEN_REG = 5;

    localparam logic [DMA_AXIL_REG_MAP_N_REGS-1:0][31:0][2:0] DMA_AXIL_REG_MAP_REG_MODE = '{

        '{REG_BIT_RO, REG_BIT_W1S, default: REG_BIT_RSVD},
        '{32{REG_BIT_RW}, default: REG_BIT_RSVD},
        '{32{REG_BIT_RW}, default: REG_BIT_RSVD},
        '{REG_BIT_RO, REG_BIT_W1S, default: REG_BIT_RSVD},
        '{32{REG_BIT_RW}, default: REG_BIT_RSVD},
        '{32{REG_BIT_RW}, default: REG_BIT_RSVD}
    };

    localparam logic [DMA_AXIL_REG_MAP_N_REGS-1:0][31:0] DMA_AXIL_REG_MAP_REG_RST = '{
        32'h0000_0000,
        32'h0000_0000,
        32'h0000_0000,
        32'h0000_0000,
        32'h0000_0000,
        32'h0000_0000
    };

endpackage