module axi4l_if_to_flat #(
  parameter int unsigned ADDR_W = 32,
  parameter int unsigned DATA_W = 32,
  parameter int unsigned USER_W = 1
)(
  axi4l_if.slave               s_axil,
  output logic [ADDR_W-1:0]   m_axil_awaddr,
  output logic [2:0]          m_axil_awprot,
  output logic [USER_W-1:0]   m_axil_awuser,
  output logic                m_axil_awvalid,
  input  logic                m_axil_awready,
  output logic [DATA_W-1:0]   m_axil_wdata,
  output logic [DATA_W/8-1:0] m_axil_wstrb,
  output logic [USER_W-1:0]   m_axil_wuser,
  output logic                m_axil_wvalid,
  input  logic                m_axil_wready,
  input  logic [1:0]          m_axil_bresp,
  input  logic [USER_W-1:0]   m_axil_buser,
  input  logic                m_axil_bvalid,
  output logic                m_axil_bready,
  output logic [ADDR_W-1:0]   m_axil_araddr,
  output logic [2:0]          m_axil_arprot,
  output logic [USER_W-1:0]   m_axil_aruser,
  output logic                m_axil_arvalid,
  input  logic                m_axil_arready,
  input  logic [DATA_W-1:0]   m_axil_rdata,
  input  logic [1:0]          m_axil_rresp,
  input  logic [USER_W-1:0]   m_axil_ruser,
  input  logic                m_axil_rvalid,
  output logic                m_axil_rready
);
  assign m_axil_awaddr        = s_axil.req.aw.addr;
  assign m_axil_awprot        = s_axil.req.aw.prot;
  assign m_axil_awuser        = s_axil.req.aw.user;
  assign m_axil_awvalid       = s_axil.req.aw.valid;
  assign s_axil.resp.aw_ready = m_axil_awready;
  assign m_axil_wdata         = s_axil.req.w.data;
  assign m_axil_wstrb         = s_axil.req.w.strb;
  assign m_axil_wuser         = s_axil.req.w.user;
  assign m_axil_wvalid        = s_axil.req.w.valid;
  assign s_axil.resp.w_ready  = m_axil_wready;
  assign s_axil.resp.b.resp   = axi_pkg::axi_resp_t'(m_axil_bresp);
  assign s_axil.resp.b.user   = m_axil_buser;
  assign s_axil.resp.b.valid  = m_axil_bvalid;
  assign m_axil_bready        = s_axil.req.b_ready;
  assign m_axil_araddr        = s_axil.req.ar.addr;
  assign m_axil_arprot        = s_axil.req.ar.prot;
  assign m_axil_aruser        = s_axil.req.ar.user;
  assign m_axil_arvalid       = s_axil.req.ar.valid;
  assign s_axil.resp.ar_ready = m_axil_arready;
  assign s_axil.resp.r.data   = m_axil_rdata;
  assign s_axil.resp.r.resp   = axi_pkg::axi_resp_t'(m_axil_rresp);
  assign s_axil.resp.r.user   = m_axil_ruser;
  assign s_axil.resp.r.valid  = m_axil_rvalid;
  assign m_axil_rready        = s_axil.req.r_ready;
endmodule