package axi4l_reg_map_example_pkg;
  import axi4l_reg_map_pkg::*;

  localparam int unsigned AXI4L_REG_MAP_EXAMPLE_N_REGS = 4;

  localparam int unsigned REG_CTRL    = 0;
  localparam int unsigned REG_STATUS  = 1;
  localparam int unsigned REG_CONFIG  = 2;
  localparam int unsigned REG_VERSION = 3;

  localparam logic [15:0] REG_CTRL_ADDR    = 16'h0000;
  localparam logic [15:0] REG_STATUS_ADDR  = 16'h0004;
  localparam logic [15:0] REG_CONFIG_ADDR  = 16'h0008;
  localparam logic [15:0] REG_VERSION_ADDR = 16'h000c;

  localparam int unsigned CTRL_START_BIT      = 0;
  localparam int unsigned CTRL_SOFT_RESET_BIT = 1;
  localparam int unsigned CTRL_ENABLE_BIT     = 2;
  localparam int unsigned CTRL_IRQ_ENABLE_BIT = 3;

  localparam int unsigned STATUS_BUSY_BIT  = 0;
  localparam int unsigned STATUS_DONE_BIT  = 1;
  localparam int unsigned STATUS_ERROR_BIT = 2;

  localparam int unsigned STATUS_ERROR_CODE_LSB = 8;
  localparam int unsigned STATUS_ERROR_CODE_MSB = 15;

  localparam logic [31:0] CONFIG_RST  = 32'h0000_0001;
  localparam logic [31:0] VERSION_VAL = 32'h0001_0000;

  localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0][2:0] AXI4L_REG_MAP_EXAMPLE_REG_MODE = '{
    REG_CTRL: '{
      CTRL_START_BIT      : REG_BIT_W1S,
      CTRL_SOFT_RESET_BIT : REG_BIT_W1S,
      CTRL_ENABLE_BIT     : REG_BIT_RW,
      CTRL_IRQ_ENABLE_BIT : REG_BIT_RW,
      default             : REG_BIT_RSVD
    },
    REG_STATUS: '{
      STATUS_BUSY_BIT       : REG_BIT_RO,
      STATUS_DONE_BIT       : REG_BIT_RO,
      STATUS_ERROR_BIT      : REG_BIT_RO,
      STATUS_ERROR_CODE_LSB : REG_BIT_RO,
      STATUS_ERROR_CODE_LSB+1 : REG_BIT_RO,
      STATUS_ERROR_CODE_LSB+2 : REG_BIT_RO,
      STATUS_ERROR_CODE_LSB+3 : REG_BIT_RO,
      STATUS_ERROR_CODE_LSB+4 : REG_BIT_RO,
      STATUS_ERROR_CODE_LSB+5 : REG_BIT_RO,
      STATUS_ERROR_CODE_LSB+6 : REG_BIT_RO,
      STATUS_ERROR_CODE_LSB+7 : REG_BIT_RO,
      default              : REG_BIT_RSVD
    },
    REG_CONFIG: '{
      default: REG_BIT_RW
    },
    REG_VERSION: '{
      default: REG_BIT_RO
    }
  };

  localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0] AXI4L_REG_MAP_EXAMPLE_REG_RST = '{
    REG_CTRL    : 32'h0000_0000,
    REG_STATUS  : 32'h0000_0000,
    REG_CONFIG  : CONFIG_RST,
    REG_VERSION : 32'h0000_0000
  };

endpackage : axi4l_reg_map_example_pkg