module axi_dma_wrapper #( parameter AXI_DATA_WIDTH = 32, parameter AXI_ADDR_WIDTH = 16, parameter AXI_ID_WIDTH = 8, parameter AXI_MAX_BURST_LEN = 16, parameter AXIS_LAST_ENABLE = 1, parameter AXIS_ID_ENABLE = 0, parameter AXIS_ID_WIDTH = 8, parameter AXIS_DEST_ENABLE = 0, parameter AXIS_DEST_WIDTH = 8, parameter AXIS_USER_ENABLE = 1, parameter AXIS_USER_WIDTH = 1, parameter LEN_WIDTH = 20, parameter TAG_WIDTH = 8, parameter ENABLE_SG = 0, parameter ENABLE_UNALIGNED = 0 )( input wire crossbar_clk, input wire crossbar_rst, input wire dma_clk, input wire dma_rst, axi4l_if.slave s_axil_control, axi4_if.master m_axi_data, output wire [AXIS_DATA_WIDTH-1:0] m_axis_read_data_tdata, output wire [AXIS_KEEP_WIDTH-1:0] m_axis_read_data_tkeep, output wire m_axis_read_data_tvalid, input wire m_axis_read_data_tready, output wire m_axis_read_data_tlast, output wire [AXIS_ID_WIDTH-1:0] m_axis_read_data_tid, output wire [AXIS_DEST_WIDTH-1:0] m_axis_read_data_tdest, output wire [AXIS_USER_WIDTH-1:0] m_axis_read_data_tuser, input wire [AXIS_DATA_WIDTH-1:0] s_axis_write_data_tdata, input wire [AXIS_KEEP_WIDTH-1:0] s_axis_write_data_tkeep, input wire s_axis_write_data_tvalid, output wire s_axis_write_data_tready, input wire s_axis_write_data_tlast, input wire [AXIS_ID_WIDTH-1:0] s_axis_write_data_tid, input wire [AXIS_DEST_WIDTH-1:0] s_axis_write_data_tdest, input wire [AXIS_USER_WIDTH-1:0] s_axis_write_data_tuser ); wire [AXI_ADDR_WIDTH-1:0] dma_s_axis_read_desc_addr; wire [LEN_WIDTH-1:0] dma_s_axis_read_desc_len; wire [TAG_WIDTH-1:0] dma_s_axis_read_desc_tag; wire [AXIS_ID_WIDTH-1:0] dma_s_axis_read_desc_id; wire [AXIS_DEST_WIDTH-1:0] dma_s_axis_read_desc_dest; wire [AXIS_USER_WIDTH-1:0] dma_s_axis_read_desc_user; wire dma_s_axis_read_desc_valid; wire dma_s_axis_read_desc_ready; wire [TAG_WIDTH-1:0] dma_m_axis_read_desc_status_tag; wire [3:0] dma_m_axis_read_desc_status_error; wire dma_m_axis_read_desc_status_valid; wire [AXI_ID_WIDTH-1:0] dma_m_axi_awid; wire [AXI_ADDR_WIDTH-1:0] dma_m_axi_awaddr; wire [7:0] dma_m_axi_awlen; wire [2:0] dma_m_axi_awsize; wire [1:0] dma_m_axi_awburst; wire dma_m_axi_awlock; wire [3:0] dma_m_axi_awcache; wire [2:0] dma_m_axi_awprot; wire dma_m_axi_awvalid; wire dma_m_axi_awready; wire [AXI_DATA_WIDTH-1:0] dma_m_axi_wdata; wire [AXI_STRB_WIDTH-1:0] dma_m_axi_wstrb; wire dma_m_axi_wlast; wire dma_m_axi_wvalid; wire dma_m_axi_wready; wire [AXI_ID_WIDTH-1:0] dma_m_axi_bid; wire [1:0] dma_m_axi_bresp; wire dma_m_axi_bvalid; wire dma_m_axi_bready; wire [AXI_ID_WIDTH-1:0] dma_m_axi_arid; wire [AXI_ADDR_WIDTH-1:0] dma_m_axi_araddr; wire [7:0] dma_m_axi_arlen; wire [2:0] dma_m_axi_arsize; wire [1:0] dma_m_axi_arburst; wire dma_m_axi_arlock; wire [3:0] dma_m_axi_arcache; wire [2:0] dma_m_axi_arprot; wire dma_m_axi_arvalid; wire dma_m_axi_arready; wire [AXI_ID_WIDTH-1:0] dma_m_axi_rid; wire [AXI_DATA_WIDTH-1:0] dma_m_axi_rdata; wire [1:0] dma_m_axi_rresp; wire dma_m_axi_rlast; wire dma_m_axi_rvalid; wire dma_m_axi_rready; wire [AXI_ADDR_WIDTH-1:0] dma_s_axis_write_desc_addr; wire [LEN_WIDTH-1:0] dma_s_axis_write_desc_len; wire [TAG_WIDTH-1:0] dma_s_axis_write_desc_tag; wire dma_s_axis_write_desc_valid; wire dma_s_axis_write_desc_ready; wire [LEN_WIDTH-1:0] dma_m_axis_write_desc_status_len; wire [TAG_WIDTH-1:0] dma_m_axis_write_desc_status_tag; wire [AXIS_ID_WIDTH-1:0] dma_m_axis_write_desc_status_id; wire [AXIS_DEST_WIDTH-1:0] dma_m_axis_write_desc_status_dest; wire [AXIS_USER_WIDTH-1:0] dma_m_axis_write_desc_status_user; wire [3:0] dma_m_axis_write_desc_status_error; wire dma_m_axis_write_desc_status_valid; wire dma_read_enable; wire dma_write_enable; wire dma_write_abort; axi4l_if #(.ADDR_W(AXI_ADDR_WIDTH), .DATA_W(AXI_DATA_WIDTH)) axi4_if_cdc (); axil_cdc_wrapper #( .ADDR_WIDTH (AXI_ADDR_WIDTH), .DATA_WIDTH (AXI_DATA_WIDTH) ) i_dma_ctrl_cdc ( .s_clk (crossbar_clk), .s_rst (crossbar_rst), .s_axi (s_axil_control), .m_clk (dma_clk), .m_rst (dma_rst), .m_axi (axi4_if_cdc) ); wire [N_REGS-1:0][31:0] reg_i; wire [N_REGS-1:0][31:0] reg_o; import dma_axil_reg_map_pkg::*; axi4l_reg_map #( .ADDR_W (AXI_ADDR_WIDTH), .DATA_W (AXI_DATA_WIDTH), .USER_W (0), .N_REGS (DMA_AXIL_REG_MAP_N_REGS), .REG_MODE (DMA_AXIL_REG_MAP_REG_MODE), .REG_RST (DMA_AXIL_REG_MAP_REG_RST) ) i_axi4l_dma_reg_map ( .clk (dma_clk), .rst_n (!dma_rst), .s_axil (axi4_if_cdc), .reg_i (reg_i), .reg_o (reg_o) ); always_comb begin dma_s_axis_write_desc_valid = reg_o[DMA_WRITE_DESC_CONTROL_REG][0]; dma_s_axis_write_desc_addr = reg_o[DMA_WRITE_DESC_ADDR_REG][31:0]; dma_s_axis_write_desc_len = reg_o[DMA_WRITE_DESC_LEN_REG][31:0]; reg_i[DMA_WRITE_DESC_CONTROL_REG][1] = dma_s_axis_write_desc_ready; dma_s_axis_read_desc_valid = reg_o[DMA_READ_DESC_CONTROL_REG][0]; dma_s_axis_read_desc_addr = reg_o[DMA_READ_DESC_ADDR_REG][31:0]; dma_s_axis_read_desc_len = reg_o[DMA_READ_DESC_LEN_REG][31:0]; reg_i[DMA_READ_DESC_CONTROL_REG][1] = dma_s_axis_read_desc_ready; end axi4_flat_to_if #( .ADDR_W (AXI_ADDR_WIDTH), .DATA_W (AXI_DATA_WIDTH) ) i_axi4_flat_to_if ( .s_axi_awid (dma_m_axi_awid), .s_axi_awaddr (dma_m_axi_awaddr), .s_axi_awlen (dma_m_axi_awlen), .s_axi_awsize (dma_m_axi_awsize), .s_axi_awburst (dma_m_axi_awburst), .s_axi_awlock (dma_m_axi_awlock), .s_axi_awcache (dma_m_axi_awcache), .s_axi_awprot (dma_m_axi_awprot), .s_axi_awqos (dma_m_axi_awqos), .s_axi_awregion (dma_m_axi_awregion), .s_axi_awuser (dma_m_axi_awuser), .s_axi_awvalid (dma_m_axi_awvalid), .s_axi_awready (dma_m_axi_awready), .s_axi_wdata (dma_m_axi_wdata), .s_axi_wstrb (dma_m_axi_wstrb), .s_axi_wlast (dma_m_axi_wlast), .s_axi_wuser (dma_m_axi_wuser), .s_axi_wvalid (dma_m_axi_wvalid), .s_axi_wready (dma_m_axi_wready), .s_axi_bid (dma_m_axi_bid), .s_axi_bresp (dma_m_axi_bresp), .s_axi_buser (dma_m_axi_buser), .s_axi_bvalid (dma_m_axi_bvalid), .s_axi_bready (dma_m_axi_bready), .s_axi_arid (dma_m_axi_arid), .s_axi_araddr (dma_m_axi_araddr), .s_axi_arlen (dma_m_axi_arlen), .s_axi_arsize (dma_m_axi_arsize), .s_axi_arburst (dma_m_axi_arburst), .s_axi_arlock (dma_m_axi_arlock), .s_axi_arcache (dma_m_axi_arcache), .s_axi_arprot (dma_m_axi_arprot), .s_axi_arqos (dma_m_axi_arqos), .s_axi_arregion (dma_m_axi_arregion), .s_axi_aruser (dma_m_axi_aruser), .s_axi_arvalid (dma_m_axi_arvalid), .s_axi_arready (dma_m_axi_arready), .s_axi_rid (dma_m_axi_rid), .s_axi_rdata (dma_m_axi_rdata), .s_axi_rresp (dma_m_axi_rresp), .s_axi_rlast (dma_m_axi_rlast), .s_axi_ruser (dma_m_axi_ruser), .s_axi_rvalid (dma_m_axi_rvalid), .s_axi_rready (dma_m_axi_rready), .m_axi (m_axi_data) ); axi_dma #( .AXI_DATA_WIDTH (AXI_DATA_WIDTH), .AXI_ADDR_WIDTH (AXI_ADDR_WIDTH), .AXI_ID_WIDTH (AXI_ID_WIDTH), .AXI_MAX_BURST_LEN (AXI_MAX_BURST_LEN), .AXIS_LAST_ENABLE (AXIS_LAST_ENABLE), .AXIS_ID_ENABLE (AXIS_ID_ENABLE), .AXIS_ID_WIDTH (AXIS_ID_WIDTH), .AXIS_DEST_ENABLE (AXIS_DEST_ENABLE), .AXIS_DEST_WIDTH (AXIS_DEST_WIDTH), .AXIS_USER_ENABLE (AXIS_USER_ENABLE), .AXIS_USER_WIDTH (AXIS_USER_WIDTH), .LEN_WIDTH (LEN_WIDTH), .TAG_WIDTH (TAG_WIDTH), .ENABLE_SG (ENABLE_SG), .ENABLE_UNALIGNED (ENABLE_UNALIGNED) ) i_axi_dma ( .clk (dma_clk), .rst (dma_rst), .s_axis_read_desc_addr (dma_s_axis_read_desc_addr), .s_axis_read_desc_len (dma_s_axis_read_desc_len), .s_axis_read_desc_tag (dma_s_axis_read_desc_tag), .s_axis_read_desc_id (dma_s_axis_read_desc_id), .s_axis_read_desc_dest (dma_s_axis_read_desc_dest), .s_axis_read_desc_user (dma_s_axis_read_desc_user), .s_axis_read_desc_valid (dma_s_axis_read_desc_valid), .s_axis_read_desc_ready (dma_s_axis_read_desc_ready), .m_axis_read_desc_status_tag (dma_m_axis_read_desc_status_tag), .m_axis_read_desc_status_error (dma_m_axis_read_desc_status_error), .m_axis_read_desc_status_valid (dma_m_axis_read_desc_status_valid), .m_axis_read_data_tdata (m_axis_read_data_tdata), .m_axis_read_data_tkeep (m_axis_read_data_tkeep), .m_axis_read_data_tvalid (m_axis_read_data_tvalid), .m_axis_read_data_tready (m_axis_read_data_tready), .m_axis_read_data_tlast (m_axis_read_data_tlast), .m_axis_read_data_tid (m_axis_read_data_tid), .m_axis_read_data_tdest (m_axis_read_data_tdest), .m_axis_read_data_tuser (m_axis_read_data_tuser), .s_axis_write_desc_addr (dma_s_axis_write_desc_addr), .s_axis_write_desc_len (dma_s_axis_write_desc_len), .s_axis_write_desc_tag (dma_s_axis_write_desc_tag), .s_axis_write_desc_valid (dma_s_axis_write_desc_valid), .s_axis_write_desc_ready (dma_s_axis_write_desc_ready), .m_axis_write_desc_status_len (dma_m_axis_write_desc_status_len), .m_axis_write_desc_status_tag (dma_m_axis_write_desc_status_tag), .m_axis_write_desc_status_id (dma_m_axis_write_desc_status_id), .m_axis_write_desc_status_dest (dma_m_axis_write_desc_status_dest), .m_axis_write_desc_status_user (dma_m_axis_write_desc_status_user), .m_axis_write_desc_status_error (dma_m_axis_write_desc_status_error), .m_axis_write_desc_status_valid (dma_m_axis_write_desc_status_valid), .s_axis_write_data_tdata (s_axis_write_data_tdata), .s_axis_write_data_tkeep (s_axis_write_data_tkeep), .s_axis_write_data_tvalid (s_axis_write_data_tvalid), .s_axis_write_data_tready (s_axis_write_data_tready), .s_axis_write_data_tlast (s_axis_write_data_tlast), .s_axis_write_data_tid (s_axis_write_data_tid), .s_axis_write_data_tdest (s_axis_write_data_tdest), .s_axis_write_data_tuser (s_axis_write_data_tuser), .m_axi_awid (dma_m_axi_awid), .m_axi_awaddr (dma_m_axi_awaddr), .m_axi_awlen (dma_m_axi_awlen), .m_axi_awsize (dma_m_axi_awsize), .m_axi_awburst (dma_m_axi_awburst), .m_axi_awlock (dma_m_axi_awlock), .m_axi_awcache (dma_m_axi_awcache), .m_axi_awprot (dma_m_axi_awprot), .m_axi_awvalid (dma_m_axi_awvalid), .m_axi_awready (dma_m_axi_awready), .m_axi_wdata (dma_m_axi_wdata), .m_axi_wstrb (dma_m_axi_wstrb), .m_axi_wlast (dma_m_axi_wlast), .m_axi_wvalid (dma_m_axi_wvalid), .m_axi_wready (dma_m_axi_wready), .m_axi_bid (dma_m_axi_bid), .m_axi_bresp (dma_m_axi_bresp), .m_axi_bvalid (dma_m_axi_bvalid), .m_axi_bready (dma_m_axi_bready), .m_axi_arid (dma_m_axi_arid), .m_axi_araddr (dma_m_axi_araddr), .m_axi_arlen (dma_m_axi_arlen), .m_axi_arsize (dma_m_axi_arsize), .m_axi_arburst (dma_m_axi_arburst), .m_axi_arlock (dma_m_axi_arlock), .m_axi_arcache (dma_m_axi_arcache), .m_axi_arprot (dma_m_axi_arprot), .m_axi_arvalid (dma_m_axi_arvalid), .m_axi_arready (dma_m_axi_arready), .m_axi_rid (dma_m_axi_rid), .m_axi_rdata (dma_m_axi_rdata), .m_axi_rresp (dma_m_axi_rresp), .m_axi_rlast (dma_m_axi_rlast), .m_axi_rvalid (dma_m_axi_rvalid), .m_axi_rready (dma_m_axi_rready), .read_enable (dma_read_enable), .write_enable (dma_write_enable), .write_abort (dma_write_abort) ); endmodule