module axi4_flat_to_if #(
  parameter int unsigned ADDR_W = 32,
  parameter int unsigned DATA_W = 64,
  parameter int unsigned ID_W   = 4,
  parameter int unsigned USER_W = 1
)(
  input  logic [ID_W-1:0]     s_axi_awid,
  input  logic [ADDR_W-1:0]   s_axi_awaddr,
  input  logic [7:0]          s_axi_awlen,
  input  logic [2:0]          s_axi_awsize,
  input  logic [1:0]          s_axi_awburst,
  input  logic                s_axi_awlock,
  input  logic [3:0]          s_axi_awcache,
  input  logic [2:0]          s_axi_awprot,
  input  logic [3:0]          s_axi_awqos,
  input  logic [3:0]          s_axi_awregion,
  input  logic [USER_W-1:0]   s_axi_awuser,
  input  logic                s_axi_awvalid,
  output logic                s_axi_awready,
  input  logic [DATA_W-1:0]   s_axi_wdata,
  input  logic [DATA_W/8-1:0] s_axi_wstrb,
  input  logic                s_axi_wlast,
  input  logic [USER_W-1:0]   s_axi_wuser,
  input  logic                s_axi_wvalid,
  output logic                s_axi_wready,
  output logic [ID_W-1:0]     s_axi_bid,
  output logic [1:0]          s_axi_bresp,
  output logic [USER_W-1:0]   s_axi_buser,
  output logic                s_axi_bvalid,
  input  logic                s_axi_bready,
  input  logic [ID_W-1:0]     s_axi_arid,
  input  logic [ADDR_W-1:0]   s_axi_araddr,
  input  logic [7:0]          s_axi_arlen,
  input  logic [2:0]          s_axi_arsize,
  input  logic [1:0]          s_axi_arburst,
  input  logic                s_axi_arlock,
  input  logic [3:0]          s_axi_arcache,
  input  logic [2:0]          s_axi_arprot,
  input  logic [3:0]          s_axi_arqos,
  input  logic [3:0]          s_axi_arregion,
  input  logic [USER_W-1:0]   s_axi_aruser,
  input  logic                s_axi_arvalid,
  output logic                s_axi_arready,
  output logic [ID_W-1:0]     s_axi_rid,
  output logic [DATA_W-1:0]   s_axi_rdata,
  output logic [1:0]          s_axi_rresp,
  output logic                s_axi_rlast,
  output logic [USER_W-1:0]   s_axi_ruser,
  output logic                s_axi_rvalid,
  input  logic                s_axi_rready,
  axi4_if.master              m_axi
);
  assign m_axi.req.aw.id      = s_axi_awid;
  assign m_axi.req.aw.addr    = s_axi_awaddr;
  assign m_axi.req.aw.len     = s_axi_awlen;
  assign m_axi.req.aw.size    = s_axi_awsize;
  assign m_axi.req.aw.burst   = axi_pkg::axi_burst_t'(s_axi_awburst);
  assign m_axi.req.aw.lock    = s_axi_awlock;
  assign m_axi.req.aw.cache   = s_axi_awcache;
  assign m_axi.req.aw.prot    = s_axi_awprot;
  assign m_axi.req.aw.qos     = s_axi_awqos;
  assign m_axi.req.aw.region  = s_axi_awregion;
  assign m_axi.req.aw.user    = s_axi_awuser;
  assign m_axi.req.aw.valid   = s_axi_awvalid;
  assign s_axi_awready        = m_axi.resp.aw_ready;
  assign m_axi.req.w.data     = s_axi_wdata;
  assign m_axi.req.w.strb     = s_axi_wstrb;
  assign m_axi.req.w.last     = s_axi_wlast;
  assign m_axi.req.w.user     = s_axi_wuser;
  assign m_axi.req.w.valid    = s_axi_wvalid;
  assign s_axi_wready         = m_axi.resp.w_ready;
  assign s_axi_bid            = m_axi.resp.b.id;
  assign s_axi_bresp          = m_axi.resp.b.resp;
  assign s_axi_buser          = m_axi.resp.b.user;
  assign s_axi_bvalid         = m_axi.resp.b.valid;
  assign m_axi.req.b_ready    = s_axi_bready;
  assign m_axi.req.ar.id      = s_axi_arid;
  assign m_axi.req.ar.addr    = s_axi_araddr;
  assign m_axi.req.ar.len     = s_axi_arlen;
  assign m_axi.req.ar.size    = s_axi_arsize;
  assign m_axi.req.ar.burst   = axi_pkg::axi_burst_t'(s_axi_arburst);
  assign m_axi.req.ar.lock    = s_axi_arlock;
  assign m_axi.req.ar.cache   = s_axi_arcache;
  assign m_axi.req.ar.prot    = s_axi_arprot;
  assign m_axi.req.ar.qos     = s_axi_arqos;
  assign m_axi.req.ar.region  = s_axi_arregion;
  assign m_axi.req.ar.user    = s_axi_aruser;
  assign m_axi.req.ar.valid   = s_axi_arvalid;
  assign s_axi_arready        = m_axi.resp.ar_ready;
  assign s_axi_rid            = m_axi.resp.r.id;
  assign s_axi_rdata          = m_axi.resp.r.data;
  assign s_axi_rresp          = m_axi.resp.r.resp;
  assign s_axi_rlast          = m_axi.resp.r.last;
  assign s_axi_ruser          = m_axi.resp.r.user;
  assign s_axi_rvalid         = m_axi.resp.r.valid;
  assign m_axi.req.r_ready    = s_axi_rready;
endmodule