package axi4l_reg_map_example_pkg;

  localparam int unsigned AXI4L_REG_MAP_EXAMPLE_N_REGS = 4;

  localparam logic [2:0] REG_BIT_RSVD = 3'd0;
  localparam logic [2:0] REG_BIT_RO   = 3'd1;
  localparam logic [2:0] REG_BIT_RW   = 3'd2;
  localparam logic [2:0] REG_BIT_W1S  = 3'd3;

  localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0][2:0] AXI4L_REG_MAP_EXAMPLE_REG_MODE = '{
    '{
      REG_BIT_W1S,
      REG_BIT_RW,
      default: REG_BIT_RSVD
    },
    '{
      REG_BIT_RO,
      default: REG_BIT_RSVD
    },
    '{
      REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO,
      REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO,
      default: REG_BIT_RSVD
    },
    '{default: REG_BIT_RW}
  };

  localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0] AXI4L_REG_MAP_EXAMPLE_REG_RST = '{
    32'h0000_0000,
    32'h0000_0000,
    32'h0000_0000,
    32'h0000_0001
  };

endpackage