package dma_axil_reg_map_pkg; localparam int unsigned DMA_AXIL_REG_MAP_N_REGS = 6; localparam int unsigned DMA_WRITE_DESC_CONTROL_REG = 0; localparam int unsigned DMA_WRITE_DESC_ADDR_REG = 1; localparam int unsigned DMA_WRITE_DESC_LEN_REG = 2; localparam int unsigned DMA_READ_DESC_CONTROL_REG = 3; localparam int unsigned DMA_READ_DESC_ADDR_REG = 4; localparam int unsigned DMA_READ_DESC_LEN_REG = 5; localparam logic [2:0] REG_BIT_RSVD = 3'd0; localparam logic [2:0] REG_BIT_RO = 3'd1; localparam logic [2:0] REG_BIT_RW = 3'd2; localparam logic [2:0] REG_BIT_W1S = 3'd3; typedef logic [DMA_AXIL_REG_MAP_N_REGS-1:0][31:0][2:0] reg_mode_map_t; function automatic reg_mode_map_t make_dma_reg_mode(); reg_mode_map_t mode; mode = '0; // По умолчанию всё reserved for (int reg_idx = 0; reg_idx < DMA_AXIL_REG_MAP_N_REGS; reg_idx++) begin for (int bit_idx = 0; bit_idx < 32; bit_idx++) begin mode[reg_idx][bit_idx] = REG_BIT_RSVD; end end // WRITE CONTROL mode[DMA_WRITE_DESC_CONTROL_REG][0] = REG_BIT_RO; mode[DMA_WRITE_DESC_CONTROL_REG][1] = REG_BIT_W1S; // WRITE ADDR for (int bit_idx = 0; bit_idx < 32; bit_idx++) begin mode[DMA_WRITE_DESC_ADDR_REG][bit_idx] = REG_BIT_RW; end // WRITE LEN for (int bit_idx = 0; bit_idx < 32; bit_idx++) begin mode[DMA_WRITE_DESC_LEN_REG][bit_idx] = REG_BIT_RW; end // READ CONTROL mode[DMA_READ_DESC_CONTROL_REG][0] = REG_BIT_RO; mode[DMA_READ_DESC_CONTROL_REG][1] = REG_BIT_W1S; // READ ADDR for (int bit_idx = 0; bit_idx < 32; bit_idx++) begin mode[DMA_READ_DESC_ADDR_REG][bit_idx] = REG_BIT_RW; end // READ LEN for (int bit_idx = 0; bit_idx < 32; bit_idx++) begin mode[DMA_READ_DESC_LEN_REG][bit_idx] = REG_BIT_RW; end return mode; endfunction localparam reg_mode_map_t DMA_AXIL_REG_MAP_REG_MODE = make_dma_reg_mode(); endpackage