module axi4_if_to_flat #(
  parameter int unsigned ADDR_W = 32,
  parameter int unsigned DATA_W = 64,
  parameter int unsigned ID_W   = 4,
  parameter int unsigned USER_W = 1
)(
  axi4_if.slave                s_axi,
  output logic [ID_W-1:0]     m_axi_awid,
  output logic [ADDR_W-1:0]   m_axi_awaddr,
  output logic [7:0]          m_axi_awlen,
  output logic [2:0]          m_axi_awsize,
  output logic [1:0]          m_axi_awburst,
  output logic                m_axi_awlock,
  output logic [3:0]          m_axi_awcache,
  output logic [2:0]          m_axi_awprot,
  output logic [3:0]          m_axi_awqos,
  output logic [3:0]          m_axi_awregion,
  output logic [USER_W-1:0]   m_axi_awuser,
  output logic                m_axi_awvalid,
  input  logic                m_axi_awready,
  output logic [DATA_W-1:0]   m_axi_wdata,
  output logic [DATA_W/8-1:0] m_axi_wstrb,
  output logic                m_axi_wlast,
  output logic [USER_W-1:0]   m_axi_wuser,
  output logic                m_axi_wvalid,
  input  logic                m_axi_wready,
  input  logic [ID_W-1:0]     m_axi_bid,
  input  logic [1:0]          m_axi_bresp,
  input  logic [USER_W-1:0]   m_axi_buser,
  input  logic                m_axi_bvalid,
  output logic                m_axi_bready,
  output logic [ID_W-1:0]     m_axi_arid,
  output logic [ADDR_W-1:0]   m_axi_araddr,
  output logic [7:0]          m_axi_arlen,
  output logic [2:0]          m_axi_arsize,
  output logic [1:0]          m_axi_arburst,
  output logic                m_axi_arlock,
  output logic [3:0]          m_axi_arcache,
  output logic [2:0]          m_axi_arprot,
  output logic [3:0]          m_axi_arqos,
  output logic [3:0]          m_axi_arregion,
  output logic [USER_W-1:0]   m_axi_aruser,
  output logic                m_axi_arvalid,
  input  logic                m_axi_arready,
  input  logic [ID_W-1:0]     m_axi_rid,
  input  logic [DATA_W-1:0]   m_axi_rdata,
  input  logic [1:0]          m_axi_rresp,
  input  logic                m_axi_rlast,
  input  logic [USER_W-1:0]   m_axi_ruser,
  input  logic                m_axi_rvalid,
  output logic                m_axi_rready
);
  assign m_axi_awid        = s_axi.req.aw.id;
  assign m_axi_awaddr      = s_axi.req.aw.addr;
  assign m_axi_awlen       = s_axi.req.aw.len;
  assign m_axi_awsize      = s_axi.req.aw.size;
  assign m_axi_awburst     = s_axi.req.aw.burst;
  assign m_axi_awlock      = s_axi.req.aw.lock;
  assign m_axi_awcache     = s_axi.req.aw.cache;
  assign m_axi_awprot      = s_axi.req.aw.prot;
  assign m_axi_awqos       = s_axi.req.aw.qos;
  assign m_axi_awregion    = s_axi.req.aw.region;
  assign m_axi_awuser      = s_axi.req.aw.user;
  assign m_axi_awvalid     = s_axi.req.aw.valid;
  assign s_axi.resp.aw_ready = m_axi_awready;
  assign m_axi_wdata       = s_axi.req.w.data;
  assign m_axi_wstrb       = s_axi.req.w.strb;
  assign m_axi_wlast       = s_axi.req.w.last;
  assign m_axi_wuser       = s_axi.req.w.user;
  assign m_axi_wvalid      = s_axi.req.w.valid;
  assign s_axi.resp.w_ready  = m_axi_wready;
  assign s_axi.resp.b.id   = m_axi_bid;
  assign s_axi.resp.b.resp = axi_pkg::axi_resp_t'(m_axi_bresp);
  assign s_axi.resp.b.user = m_axi_buser;
  assign s_axi.resp.b.valid= m_axi_bvalid;
  assign m_axi_bready      = s_axi.req.b_ready;
  assign m_axi_arid        = s_axi.req.ar.id;
  assign m_axi_araddr      = s_axi.req.ar.addr;
  assign m_axi_arlen       = s_axi.req.ar.len;
  assign m_axi_arsize      = s_axi.req.ar.size;
  assign m_axi_arburst     = s_axi.req.ar.burst;
  assign m_axi_arlock      = s_axi.req.ar.lock;
  assign m_axi_arcache     = s_axi.req.ar.cache;
  assign m_axi_arprot      = s_axi.req.ar.prot;
  assign m_axi_arqos       = s_axi.req.ar.qos;
  assign m_axi_arregion    = s_axi.req.ar.region;
  assign m_axi_aruser      = s_axi.req.ar.user;
  assign m_axi_arvalid     = s_axi.req.ar.valid;
  assign s_axi.resp.ar_ready = m_axi_arready;
  assign s_axi.resp.r.id   = m_axi_rid;
  assign s_axi.resp.r.data = m_axi_rdata;
  assign s_axi.resp.r.resp = axi_pkg::axi_resp_t'(m_axi_rresp);
  assign s_axi.resp.r.last = m_axi_rlast;
  assign s_axi.resp.r.user = m_axi_ruser;
  assign s_axi.resp.r.valid= m_axi_rvalid;
  assign m_axi_rready      = s_axi.req.r_ready;
endmodule