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cocotb_pro
| Author | SHA1 | Date | |
|---|---|---|---|
| 4dac1789c8 |
430
axi/tb/axi_cocotb_loopback_test/axi4_proxy.py
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430
axi/tb/axi_cocotb_loopback_test/axi4_proxy.py
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@ -0,0 +1,430 @@
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# proxy to match cocotb and custom axi4_if
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import logging
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from cocotb.types import LogicArray
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from cocotbext.axi.axi_channels import (
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AxiAWBus,
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AxiWBus,
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AxiBBus,
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AxiARBus,
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AxiRBus,
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AxiBus,
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)
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def install_cocotbext_axi_slice_compat():
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"""
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cocotbext-axi StreamMonitor uses RisingEdge(self.valid/self.ready).
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That works only for real cocotb LogicObject handles.
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Our SliceSignal is a Python proxy over packed req/resp vector, so
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RisingEdge(SliceSignal) fails in cocotb 2.x.
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This patch makes StreamMonitor wake on signal.value_change instead.
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For SliceSignal this should return parent packed vector value_change.
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"""
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# this sucks...
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from cocotbext.axi import stream as axi_stream
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async def _run_valid_monitor_value_change(self):
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while True:
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await self.valid.value_change
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self.wake_event.set()
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async def _run_ready_monitor_value_change(self):
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while True:
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await self.ready.value_change
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self.wake_event.set()
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axi_stream.StreamMonitor._run_valid_monitor = _run_valid_monitor_value_change
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axi_stream.StreamMonitor._run_ready_monitor = _run_ready_monitor_value_change
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def _safe_int(value) -> int:
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try:
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return int(value)
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except Exception:
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s = str(value).upper()
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bits = []
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for ch in s:
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if ch in "01":
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bits.append(ch)
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elif ch in "XZUW-":
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bits.append("0")
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if not bits:
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return 0
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return int("".join(bits), 2)
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def _logic_array(value: int, width: int):
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value &= (1 << width) - 1
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return LogicArray.from_unsigned(value, width)
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def _param_int(obj, name: str, override):
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if override is not None:
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return int(override)
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p = getattr(obj, name)
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try:
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return int(p)
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except Exception:
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pass
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try:
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return int(p.value)
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except Exception:
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pass
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raise RuntimeError(f"Cannot read parameter {name} from {obj!r}")
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def _packed_offsets(fields):
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"""
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de-construct SV signal order.
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"""
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total = sum(width for _, width in fields)
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pos = total
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offsets = {}
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for name, width in fields:
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pos -= width
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offsets[name] = (pos, width)
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return total, offsets
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class PackedVector:
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def __init__(self, handle, name=None):
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self.handle = handle
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self.name = name or getattr(handle, "_path", repr(handle))
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self.width = len(handle)
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self.mask = (1 << self.width) - 1
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self.shadow = _safe_int(handle.value) & self.mask
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self.dirty = False
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def read(self, lo: int, width: int) -> int:
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src = self.shadow if self.dirty else (
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_safe_int(self.handle.value) & self.mask)
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return (src >> lo) & ((1 << width) - 1)
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def write(self, lo: int, width: int, value, immediate=False):
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value = _safe_int(value)
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field_mask = ((1 << width) - 1) << lo
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self.shadow &= ~field_mask
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self.shadow |= (value << lo) & field_mask
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self.shadow &= self.mask
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self.dirty = True
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v = _logic_array(self.shadow, self.width)
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if immediate:
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self.handle.setimmediatevalue(v)
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else:
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self.handle.value = v
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class SliceSignal:
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"""
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cocotbext-axi proxy
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looks like:
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sig.value
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sig.value = ...
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sig.setimmediatevalue(...)
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len(sig)
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"""
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def __init__(self, name: str, parent: PackedVector, lo: int, width: int):
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self._name = name
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self._path = name
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self._log = logging.getLogger(f"cocotb.{name}")
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self.parent = parent
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self.lo = lo
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self.width = width
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def __len__(self):
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return self.width
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def __repr__(self):
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return f"<SliceSignal {self._path}[{self.lo + self.width - 1}:{self.lo}]>"
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@property
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def value(self):
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return _logic_array(self.parent.read(self.lo, self.width), self.width)
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@value.setter
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def value(self, value):
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self.parent.write(self.lo, self.width, value, immediate=False)
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def setimmediatevalue(self, value):
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self.parent.write(self.lo, self.width, value, immediate=True)
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def set(self, value):
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self.value = value
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def get(self):
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return self.value
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@property
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def value_change(self):
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# dirty
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return self.parent.handle.value_change
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class ProxyEntity:
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def __init__(self, name: str, **signals):
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self._name = name
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self._path = name
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self._log = logging.getLogger(f"cocotb.{name}")
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self.__dict__.update(signals)
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def __dir__(self):
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return list(self.__dict__.keys())
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def _sig(name, parent, base_lo, layout, field):
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lo, width = layout[field]
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return SliceSignal(name, parent, base_lo + lo, width)
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def axi4_bus_from_packed_if(
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iface,
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name="axi",
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*,
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addr_width=None,
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data_width=None,
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id_width=None,
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user_width=None,
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):
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"""
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Build cocotbext-axi AxiBus from custom packed axi4_if.
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iface should be instance axi4_if:
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dut.axi_in
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dut.axi_out
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example:
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master = AxiMaster(
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axi4_bus_from_packed_if(dut.axi_in, "s_axi"),
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dut.clk,
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dut.rst,
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)
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ram = AxiRam(
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axi4_bus_from_packed_if(dut.axi_out, "m_axi"),
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dut.clk,
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dut.rst,
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size=2**20,
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)
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"""
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ADDR_W = _param_int(iface, "ADDR_W", addr_width)
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DATA_W = _param_int(iface, "DATA_W", data_width)
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ID_W = _param_int(iface, "ID_W", id_width)
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USER_W = _param_int(iface, "USER_W", user_width)
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if DATA_W % 8 != 0:
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raise ValueError(f"AXI DATA_W must be divisible by 8, got {DATA_W}")
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STRB_W = DATA_W // 8
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aw_total, aw_layout = _packed_offsets([
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("id", ID_W),
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("addr", ADDR_W),
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("len", 8),
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("size", 3),
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("burst", 2),
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("lock", 1),
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("cache", 4),
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("prot", 3),
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("qos", 4),
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("region", 4),
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("user", USER_W),
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("valid", 1),
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])
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w_total, w_layout = _packed_offsets([
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("data", DATA_W),
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("strb", STRB_W),
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("last", 1),
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("user", USER_W),
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("valid", 1),
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])
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b_total, b_layout = _packed_offsets([
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("id", ID_W),
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("resp", 2),
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("user", USER_W),
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("valid", 1),
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])
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ar_total, ar_layout = _packed_offsets([
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("id", ID_W),
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("addr", ADDR_W),
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("len", 8),
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("size", 3),
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("burst", 2),
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("lock", 1),
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("cache", 4),
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("prot", 3),
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("qos", 4),
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("region", 4),
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("user", USER_W),
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("valid", 1),
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])
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r_total, r_layout = _packed_offsets([
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("id", ID_W),
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("data", DATA_W),
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("resp", 2),
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("last", 1),
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("user", USER_W),
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("valid", 1),
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])
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req_total, req_layout = _packed_offsets([
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("aw", aw_total),
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("w", w_total),
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("b_ready", 1),
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("ar", ar_total),
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("r_ready", 1),
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])
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resp_total, resp_layout = _packed_offsets([
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("aw_ready", 1),
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("w_ready", 1),
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("b", b_total),
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("ar_ready", 1),
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("r", r_total),
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])
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req = PackedVector(iface.req, f"{name}.req")
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resp = PackedVector(iface.resp, f"{name}.resp")
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if req_total != req.width:
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raise RuntimeError(
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f"{name}.req layout mismatch: calculated {req_total} bits, "
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f"simulator has {req.width} bits"
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)
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if resp_total != resp.width:
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raise RuntimeError(
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f"{name}.resp layout mismatch: calculated {resp_total} bits, "
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f"simulator has {resp.width} bits"
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)
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aw_lo, _ = req_layout["aw"]
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w_lo, _ = req_layout["w"]
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ar_lo, _ = req_layout["ar"]
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b_lo, _ = resp_layout["b"]
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r_lo, _ = resp_layout["r"]
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aw = AxiAWBus.from_entity(ProxyEntity(
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f"{name}_aw",
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awid=_sig(f"{name}_awid", req, aw_lo, aw_layout, "id"),
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awaddr=_sig(f"{name}_awaddr", req, aw_lo, aw_layout, "addr"),
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awlen=_sig(f"{name}_awlen", req, aw_lo, aw_layout, "len"),
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awsize=_sig(f"{name}_awsize", req, aw_lo, aw_layout, "size"),
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awburst=_sig(f"{name}_awburst", req, aw_lo, aw_layout, "burst"),
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awlock=_sig(f"{name}_awlock", req, aw_lo, aw_layout, "lock"),
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awcache=_sig(f"{name}_awcache", req, aw_lo, aw_layout, "cache"),
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awprot=_sig(f"{name}_awprot", req, aw_lo, aw_layout, "prot"),
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awqos=_sig(f"{name}_awqos", req, aw_lo, aw_layout, "qos"),
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awregion=_sig(f"{name}_awregion", req, aw_lo, aw_layout, "region"),
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awuser=_sig(f"{name}_awuser", req, aw_lo, aw_layout, "user"),
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awvalid=_sig(f"{name}_awvalid", req, aw_lo, aw_layout, "valid"),
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awready=SliceSignal(
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f"{name}_awready",
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resp,
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*resp_layout["aw_ready"],
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),
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))
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w = AxiWBus.from_entity(ProxyEntity(
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f"{name}_w",
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wdata=_sig(f"{name}_wdata", req, w_lo, w_layout, "data"),
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wstrb=_sig(f"{name}_wstrb", req, w_lo, w_layout, "strb"),
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wlast=_sig(f"{name}_wlast", req, w_lo, w_layout, "last"),
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wuser=_sig(f"{name}_wuser", req, w_lo, w_layout, "user"),
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wvalid=_sig(f"{name}_wvalid", req, w_lo, w_layout, "valid"),
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wready=SliceSignal(
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f"{name}_wready",
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resp,
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*resp_layout["w_ready"],
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),
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))
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b = AxiBBus.from_entity(ProxyEntity(
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f"{name}_b",
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bid=_sig(f"{name}_bid", resp, b_lo, b_layout, "id"),
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bresp=_sig(f"{name}_bresp", resp, b_lo, b_layout, "resp"),
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buser=_sig(f"{name}_buser", resp, b_lo, b_layout, "user"),
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bvalid=_sig(f"{name}_bvalid", resp, b_lo, b_layout, "valid"),
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bready=SliceSignal(
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f"{name}_bready",
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req,
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*req_layout["b_ready"],
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),
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))
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ar = AxiARBus.from_entity(ProxyEntity(
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f"{name}_ar",
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arid=_sig(f"{name}_arid", req, ar_lo, ar_layout, "id"),
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araddr=_sig(f"{name}_araddr", req, ar_lo, ar_layout, "addr"),
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arlen=_sig(f"{name}_arlen", req, ar_lo, ar_layout, "len"),
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arsize=_sig(f"{name}_arsize", req, ar_lo, ar_layout, "size"),
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arburst=_sig(f"{name}_arburst", req, ar_lo, ar_layout, "burst"),
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arlock=_sig(f"{name}_arlock", req, ar_lo, ar_layout, "lock"),
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arcache=_sig(f"{name}_arcache", req, ar_lo, ar_layout, "cache"),
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arprot=_sig(f"{name}_arprot", req, ar_lo, ar_layout, "prot"),
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arqos=_sig(f"{name}_arqos", req, ar_lo, ar_layout, "qos"),
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arregion=_sig(f"{name}_arregion", req, ar_lo, ar_layout, "region"),
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aruser=_sig(f"{name}_aruser", req, ar_lo, ar_layout, "user"),
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arvalid=_sig(f"{name}_arvalid", req, ar_lo, ar_layout, "valid"),
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arready=SliceSignal(
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f"{name}_arready",
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resp,
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*resp_layout["ar_ready"],
|
||||
),
|
||||
))
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r = AxiRBus.from_entity(ProxyEntity(
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f"{name}_r",
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rid=_sig(f"{name}_rid", resp, r_lo, r_layout, "id"),
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rdata=_sig(f"{name}_rdata", resp, r_lo, r_layout, "data"),
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rresp=_sig(f"{name}_rresp", resp, r_lo, r_layout, "resp"),
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rlast=_sig(f"{name}_rlast", resp, r_lo, r_layout, "last"),
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ruser=_sig(f"{name}_ruser", resp, r_lo, r_layout, "user"),
|
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rvalid=_sig(f"{name}_rvalid", resp, r_lo, r_layout, "valid"),
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|
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rready=SliceSignal(
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f"{name}_rready",
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req,
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*req_layout["r_ready"],
|
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),
|
||||
))
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return AxiBus.from_channels(aw, w, b, ar, r)
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@ -1,113 +1,11 @@
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`timescale 1ns/1ps
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|
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module tb_axi4_loopback #(
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parameter int unsigned ADDR_W = 32,
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parameter int unsigned DATA_W = 64,
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parameter int unsigned ID_W = 4,
|
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parameter int unsigned USER_W = 1
|
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)(
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input logic clk,
|
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input logic rst,
|
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|
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// slave-side flat AXI port (cocotb driven)
|
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input logic [ID_W-1:0] s_axi_awid,
|
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input logic [ADDR_W-1:0] s_axi_awaddr,
|
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input logic [7:0] s_axi_awlen,
|
||||
input logic [2:0] s_axi_awsize,
|
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input logic [1:0] s_axi_awburst,
|
||||
input logic s_axi_awlock,
|
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input logic [3:0] s_axi_awcache,
|
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input logic [2:0] s_axi_awprot,
|
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input logic [3:0] s_axi_awqos,
|
||||
input logic [3:0] s_axi_awregion,
|
||||
input logic [USER_W-1:0] s_axi_awuser,
|
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input logic s_axi_awvalid,
|
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output logic s_axi_awready,
|
||||
|
||||
input logic [DATA_W-1:0] s_axi_wdata,
|
||||
input logic [DATA_W/8-1:0] s_axi_wstrb,
|
||||
input logic s_axi_wlast,
|
||||
input logic [USER_W-1:0] s_axi_wuser,
|
||||
input logic s_axi_wvalid,
|
||||
output logic s_axi_wready,
|
||||
|
||||
output logic [ID_W-1:0] s_axi_bid,
|
||||
output logic [1:0] s_axi_bresp,
|
||||
output logic [USER_W-1:0] s_axi_buser,
|
||||
output logic s_axi_bvalid,
|
||||
input logic s_axi_bready,
|
||||
|
||||
input logic [ID_W-1:0] s_axi_arid,
|
||||
input logic [ADDR_W-1:0] s_axi_araddr,
|
||||
input logic [7:0] s_axi_arlen,
|
||||
input logic [2:0] s_axi_arsize,
|
||||
input logic [1:0] s_axi_arburst,
|
||||
input logic s_axi_arlock,
|
||||
input logic [3:0] s_axi_arcache,
|
||||
input logic [2:0] s_axi_arprot,
|
||||
input logic [3:0] s_axi_arqos,
|
||||
input logic [3:0] s_axi_arregion,
|
||||
input logic [USER_W-1:0] s_axi_aruser,
|
||||
input logic s_axi_arvalid,
|
||||
output logic s_axi_arready,
|
||||
|
||||
output logic [ID_W-1:0] s_axi_rid,
|
||||
output logic [DATA_W-1:0] s_axi_rdata,
|
||||
output logic [1:0] s_axi_rresp,
|
||||
output logic s_axi_rlast,
|
||||
output logic [USER_W-1:0] s_axi_ruser,
|
||||
output logic s_axi_rvalid,
|
||||
input logic s_axi_rready,
|
||||
|
||||
// master-side flat AXI port for coco-tb
|
||||
output logic [ID_W-1:0] m_axi_awid,
|
||||
output logic [ADDR_W-1:0] m_axi_awaddr,
|
||||
output logic [7:0] m_axi_awlen,
|
||||
output logic [2:0] m_axi_awsize,
|
||||
output logic [1:0] m_axi_awburst,
|
||||
output logic m_axi_awlock,
|
||||
output logic [3:0] m_axi_awcache,
|
||||
output logic [2:0] m_axi_awprot,
|
||||
output logic [3:0] m_axi_awqos,
|
||||
output logic [3:0] m_axi_awregion,
|
||||
output logic [USER_W-1:0] m_axi_awuser,
|
||||
output logic m_axi_awvalid,
|
||||
input logic m_axi_awready,
|
||||
|
||||
output logic [DATA_W-1:0] m_axi_wdata,
|
||||
output logic [DATA_W/8-1:0] m_axi_wstrb,
|
||||
output logic m_axi_wlast,
|
||||
output logic [USER_W-1:0] m_axi_wuser,
|
||||
output logic m_axi_wvalid,
|
||||
input logic m_axi_wready,
|
||||
|
||||
input logic [ID_W-1:0] m_axi_bid,
|
||||
input logic [1:0] m_axi_bresp,
|
||||
input logic [USER_W-1:0] m_axi_buser,
|
||||
input logic m_axi_bvalid,
|
||||
output logic m_axi_bready,
|
||||
|
||||
output logic [ID_W-1:0] m_axi_arid,
|
||||
output logic [ADDR_W-1:0] m_axi_araddr,
|
||||
output logic [7:0] m_axi_arlen,
|
||||
output logic [2:0] m_axi_arsize,
|
||||
output logic [1:0] m_axi_arburst,
|
||||
output logic m_axi_arlock,
|
||||
output logic [3:0] m_axi_arcache,
|
||||
output logic [2:0] m_axi_arprot,
|
||||
output logic [3:0] m_axi_arqos,
|
||||
output logic [3:0] m_axi_arregion,
|
||||
output logic [USER_W-1:0] m_axi_aruser,
|
||||
output logic m_axi_arvalid,
|
||||
input logic m_axi_arready,
|
||||
|
||||
input logic [ID_W-1:0] m_axi_rid,
|
||||
input logic [DATA_W-1:0] m_axi_rdata,
|
||||
input logic [1:0] m_axi_rresp,
|
||||
input logic m_axi_rlast,
|
||||
input logic [USER_W-1:0] m_axi_ruser,
|
||||
input logic m_axi_rvalid,
|
||||
output logic m_axi_rready
|
||||
input logic clk,
|
||||
input logic rst
|
||||
);
|
||||
|
||||
logic aresetn;
|
||||
@ -133,120 +31,9 @@ module tb_axi4_loopback #(
|
||||
.aresetn(aresetn)
|
||||
);
|
||||
|
||||
axi4_flat_to_if #(
|
||||
.ADDR_W(ADDR_W),
|
||||
.DATA_W(DATA_W),
|
||||
.ID_W(ID_W),
|
||||
.USER_W(USER_W)
|
||||
) u_flat_to_if (
|
||||
.s_axi_awid (s_axi_awid),
|
||||
.s_axi_awaddr (s_axi_awaddr),
|
||||
.s_axi_awlen (s_axi_awlen),
|
||||
.s_axi_awsize (s_axi_awsize),
|
||||
.s_axi_awburst (s_axi_awburst),
|
||||
.s_axi_awlock (s_axi_awlock),
|
||||
.s_axi_awcache (s_axi_awcache),
|
||||
.s_axi_awprot (s_axi_awprot),
|
||||
.s_axi_awqos (s_axi_awqos),
|
||||
.s_axi_awregion (s_axi_awregion),
|
||||
.s_axi_awuser (s_axi_awuser),
|
||||
.s_axi_awvalid (s_axi_awvalid),
|
||||
.s_axi_awready (s_axi_awready),
|
||||
.s_axi_wdata (s_axi_wdata),
|
||||
.s_axi_wstrb (s_axi_wstrb),
|
||||
.s_axi_wlast (s_axi_wlast),
|
||||
.s_axi_wuser (s_axi_wuser),
|
||||
.s_axi_wvalid (s_axi_wvalid),
|
||||
.s_axi_wready (s_axi_wready),
|
||||
.s_axi_bid (s_axi_bid),
|
||||
.s_axi_bresp (s_axi_bresp),
|
||||
.s_axi_buser (s_axi_buser),
|
||||
.s_axi_bvalid (s_axi_bvalid),
|
||||
.s_axi_bready (s_axi_bready),
|
||||
.s_axi_arid (s_axi_arid),
|
||||
.s_axi_araddr (s_axi_araddr),
|
||||
.s_axi_arlen (s_axi_arlen),
|
||||
.s_axi_arsize (s_axi_arsize),
|
||||
.s_axi_arburst (s_axi_arburst),
|
||||
.s_axi_arlock (s_axi_arlock),
|
||||
.s_axi_arcache (s_axi_arcache),
|
||||
.s_axi_arprot (s_axi_arprot),
|
||||
.s_axi_arqos (s_axi_arqos),
|
||||
.s_axi_arregion (s_axi_arregion),
|
||||
.s_axi_aruser (s_axi_aruser),
|
||||
.s_axi_arvalid (s_axi_arvalid),
|
||||
.s_axi_arready (s_axi_arready),
|
||||
.s_axi_rid (s_axi_rid),
|
||||
.s_axi_rdata (s_axi_rdata),
|
||||
.s_axi_rresp (s_axi_rresp),
|
||||
.s_axi_rlast (s_axi_rlast),
|
||||
.s_axi_ruser (s_axi_ruser),
|
||||
.s_axi_rvalid (s_axi_rvalid),
|
||||
.s_axi_rready (s_axi_rready),
|
||||
.m_axi (axi_in)
|
||||
);
|
||||
|
||||
axi4_loopback #(
|
||||
.ADDR_W(ADDR_W),
|
||||
.DATA_W(DATA_W),
|
||||
.ID_W(ID_W),
|
||||
.USER_W(USER_W)
|
||||
) dut (
|
||||
axi4_loopback dut (
|
||||
.s_axi(axi_in),
|
||||
.m_axi(axi_out)
|
||||
);
|
||||
|
||||
axi4_if_to_flat #(
|
||||
.ADDR_W(ADDR_W),
|
||||
.DATA_W(DATA_W),
|
||||
.ID_W(ID_W),
|
||||
.USER_W(USER_W)
|
||||
) u_if_to_flat (
|
||||
.s_axi (axi_out),
|
||||
.m_axi_awid (m_axi_awid),
|
||||
.m_axi_awaddr (m_axi_awaddr),
|
||||
.m_axi_awlen (m_axi_awlen),
|
||||
.m_axi_awsize (m_axi_awsize),
|
||||
.m_axi_awburst (m_axi_awburst),
|
||||
.m_axi_awlock (m_axi_awlock),
|
||||
.m_axi_awcache (m_axi_awcache),
|
||||
.m_axi_awprot (m_axi_awprot),
|
||||
.m_axi_awqos (m_axi_awqos),
|
||||
.m_axi_awregion (m_axi_awregion),
|
||||
.m_axi_awuser (m_axi_awuser),
|
||||
.m_axi_awvalid (m_axi_awvalid),
|
||||
.m_axi_awready (m_axi_awready),
|
||||
.m_axi_wdata (m_axi_wdata),
|
||||
.m_axi_wstrb (m_axi_wstrb),
|
||||
.m_axi_wlast (m_axi_wlast),
|
||||
.m_axi_wuser (m_axi_wuser),
|
||||
.m_axi_wvalid (m_axi_wvalid),
|
||||
.m_axi_wready (m_axi_wready),
|
||||
.m_axi_bid (m_axi_bid),
|
||||
.m_axi_bresp (m_axi_bresp),
|
||||
.m_axi_buser (m_axi_buser),
|
||||
.m_axi_bvalid (m_axi_bvalid),
|
||||
.m_axi_bready (m_axi_bready),
|
||||
.m_axi_arid (m_axi_arid),
|
||||
.m_axi_araddr (m_axi_araddr),
|
||||
.m_axi_arlen (m_axi_arlen),
|
||||
.m_axi_arsize (m_axi_arsize),
|
||||
.m_axi_arburst (m_axi_arburst),
|
||||
.m_axi_arlock (m_axi_arlock),
|
||||
.m_axi_arcache (m_axi_arcache),
|
||||
.m_axi_arprot (m_axi_arprot),
|
||||
.m_axi_arqos (m_axi_arqos),
|
||||
.m_axi_arregion (m_axi_arregion),
|
||||
.m_axi_aruser (m_axi_aruser),
|
||||
.m_axi_arvalid (m_axi_arvalid),
|
||||
.m_axi_arready (m_axi_arready),
|
||||
.m_axi_rid (m_axi_rid),
|
||||
.m_axi_rdata (m_axi_rdata),
|
||||
.m_axi_rresp (m_axi_rresp),
|
||||
.m_axi_rlast (m_axi_rlast),
|
||||
.m_axi_ruser (m_axi_ruser),
|
||||
.m_axi_rvalid (m_axi_rvalid),
|
||||
.m_axi_rready (m_axi_rready)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@ -3,7 +3,12 @@ import itertools
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge, Timer
|
||||
from cocotbext.axi import AxiBus, AxiMaster, AxiRam
|
||||
from cocotbext.axi import AxiMaster, AxiRam
|
||||
|
||||
from cocotbext.axi import AxiMaster, AxiRam
|
||||
from axi4_proxy import axi4_bus_from_packed_if, install_cocotbext_axi_slice_compat
|
||||
|
||||
install_cocotbext_axi_slice_compat()
|
||||
|
||||
|
||||
class TB:
|
||||
@ -12,21 +17,28 @@ class TB:
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
|
||||
|
||||
# Forencich-style connection:
|
||||
# s_axi: cocotb AXI master -> flat_to_if -> compact AXI interface
|
||||
# m_axi: compact AXI interface -> if_to_flat -> cocotb AXI RAM
|
||||
self.master = AxiMaster(AxiBus.from_prefix(
|
||||
dut, "s_axi"), dut.clk, dut.rst)
|
||||
self.ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"),
|
||||
dut.clk, dut.rst, size=2**20)
|
||||
self.master = AxiMaster(
|
||||
axi4_bus_from_packed_if(dut.axi_in, "s_axi"),
|
||||
dut.clk,
|
||||
dut.rst,
|
||||
)
|
||||
|
||||
self.ram = AxiRam(
|
||||
axi4_bus_from_packed_if(dut.axi_out, "m_axi"),
|
||||
dut.clk,
|
||||
dut.rst,
|
||||
size=2**20,
|
||||
)
|
||||
|
||||
async def reset(self):
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
self.dut.rst.value = 1
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
self.dut.rst.value = 0
|
||||
await RisingEdge(self.dut.clk)
|
||||
await RisingEdge(self.dut.clk)
|
||||
@ -36,6 +48,13 @@ def cycle_pause():
|
||||
return itertools.cycle([1, 1, 1, 0])
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def inspect_axi_if(dut):
|
||||
dut._log.info("axi_in fields: %s", dir(dut.axi_in))
|
||||
dut._log.info("axi_in.req fields: %s", dir(dut.axi_in.req))
|
||||
dut._log.info("axi_in.resp fields: %s", dir(dut.axi_in.resp))
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_basic_write_read_test(dut):
|
||||
# simple loopback test..
|
||||
|
||||
Reference in New Issue
Block a user