From fbfb869f00beba2baa7b195a127468df1c63ac65 Mon Sep 17 00:00:00 2001 From: Phil Date: Tue, 9 Jun 2026 18:07:42 +0300 Subject: [PATCH] tests: add test wrapper flat2if --- axi/tb/axi_dma_wrapper/tb_axi_dma_wrapper.sv | 355 +++++++++++++++++++ 1 file changed, 355 insertions(+) create mode 100644 axi/tb/axi_dma_wrapper/tb_axi_dma_wrapper.sv diff --git a/axi/tb/axi_dma_wrapper/tb_axi_dma_wrapper.sv b/axi/tb/axi_dma_wrapper/tb_axi_dma_wrapper.sv new file mode 100644 index 0000000..bd3f6e0 --- /dev/null +++ b/axi/tb/axi_dma_wrapper/tb_axi_dma_wrapper.sv @@ -0,0 +1,355 @@ +// SPDX-License-Identifier: MIT +// +// Cocotb-facing test top for axi_dma_if_wrapper. +// +// Cocotb still sees flat Forencich-style signal names. Internally this top +// converts those flat signals to local interfaces, passes them through the +// wrapper, and converts the wrapper interfaces back to flat signals. + +`default_nettype none + +module tb_axi_dma_wrapper #( + parameter int unsigned AXI_DATA_WIDTH = 32, + parameter int unsigned AXI_ADDR_WIDTH = 16, + parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8, + parameter int unsigned AXI_ID_WIDTH = 8, + parameter int unsigned AXI_USER_WIDTH = 1, + parameter int unsigned AXI_MAX_BURST_LEN = 16, + + parameter int unsigned AXIS_DATA_WIDTH = AXI_DATA_WIDTH, + parameter int unsigned AXIS_KEEP_ENABLE = AXIS_DATA_WIDTH > 8, + parameter int unsigned AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH / 8, + parameter int unsigned AXIS_LAST_ENABLE = 1, + parameter int unsigned AXIS_ID_ENABLE = 1, + parameter int unsigned AXIS_ID_WIDTH = 8, + parameter int unsigned AXIS_DEST_ENABLE = 0, + parameter int unsigned AXIS_DEST_WIDTH = 8, + parameter int unsigned AXIS_USER_ENABLE = 1, + parameter int unsigned AXIS_USER_WIDTH = 1, + + parameter int unsigned LEN_WIDTH = 20, + parameter int unsigned TAG_WIDTH = 8, + parameter int unsigned ENABLE_SG = 0, + parameter int unsigned ENABLE_UNALIGNED = 0 +)(); + + // cocotb drives these directly + logic clk; + logic rst; + logic rstn; + + assign rstn = ~rst; + + // -------------------------------------------------------------------------- + // Flat descriptor/status ports visible to cocotb + // -------------------------------------------------------------------------- + + logic [AXI_ADDR_WIDTH-1:0] s_axis_read_desc_addr; + logic [LEN_WIDTH-1:0] s_axis_read_desc_len; + logic [TAG_WIDTH-1:0] s_axis_read_desc_tag; + logic [AXIS_ID_WIDTH-1:0] s_axis_read_desc_id; + logic [AXIS_DEST_WIDTH-1:0] s_axis_read_desc_dest; + logic [AXIS_USER_WIDTH-1:0] s_axis_read_desc_user; + logic s_axis_read_desc_valid; + logic s_axis_read_desc_ready; + + logic [TAG_WIDTH-1:0] m_axis_read_desc_status_tag; + logic [3:0] m_axis_read_desc_status_error; + logic m_axis_read_desc_status_valid; + + logic [AXI_ADDR_WIDTH-1:0] s_axis_write_desc_addr; + logic [LEN_WIDTH-1:0] s_axis_write_desc_len; + logic [TAG_WIDTH-1:0] s_axis_write_desc_tag; + logic s_axis_write_desc_valid; + logic s_axis_write_desc_ready; + + logic [LEN_WIDTH-1:0] m_axis_write_desc_status_len; + logic [TAG_WIDTH-1:0] m_axis_write_desc_status_tag; + logic [AXIS_ID_WIDTH-1:0] m_axis_write_desc_status_id; + logic [AXIS_DEST_WIDTH-1:0] m_axis_write_desc_status_dest; + logic [AXIS_USER_WIDTH-1:0] m_axis_write_desc_status_user; + logic [3:0] m_axis_write_desc_status_error; + logic m_axis_write_desc_status_valid; + + // -------------------------------------------------------------------------- + // Flat AXIS data ports visible to cocotb + // -------------------------------------------------------------------------- + + logic [AXIS_DATA_WIDTH-1:0] m_axis_read_data_tdata; + logic [AXIS_KEEP_WIDTH-1:0] m_axis_read_data_tkeep; + logic [AXIS_KEEP_WIDTH-1:0] m_axis_read_data_tstrb; + logic m_axis_read_data_tvalid; + logic m_axis_read_data_tready; + logic m_axis_read_data_tlast; + logic [AXIS_ID_WIDTH-1:0] m_axis_read_data_tid; + logic [AXIS_DEST_WIDTH-1:0] m_axis_read_data_tdest; + logic [AXIS_USER_WIDTH-1:0] m_axis_read_data_tuser; + + logic [AXIS_DATA_WIDTH-1:0] s_axis_write_data_tdata; + logic [AXIS_KEEP_WIDTH-1:0] s_axis_write_data_tkeep; + logic [AXIS_KEEP_WIDTH-1:0] s_axis_write_data_tstrb; + logic s_axis_write_data_tvalid; + logic s_axis_write_data_tready; + logic s_axis_write_data_tlast; + logic [AXIS_ID_WIDTH-1:0] s_axis_write_data_tid; + logic [AXIS_DEST_WIDTH-1:0] s_axis_write_data_tdest; + logic [AXIS_USER_WIDTH-1:0] s_axis_write_data_tuser; + + // -------------------------------------------------------------------------- + // Flat AXI memory master ports visible to cocotb AxiRam + // -------------------------------------------------------------------------- + + logic [AXI_ID_WIDTH-1:0] m_axi_awid; + logic [AXI_ADDR_WIDTH-1:0] m_axi_awaddr; + logic [7:0] m_axi_awlen; + logic [2:0] m_axi_awsize; + logic [1:0] m_axi_awburst; + logic m_axi_awlock; + logic [3:0] m_axi_awcache; + logic [2:0] m_axi_awprot; + logic [3:0] m_axi_awqos; + logic [3:0] m_axi_awregion; + logic [AXI_USER_WIDTH-1:0] m_axi_awuser; + logic m_axi_awvalid; + logic m_axi_awready; + + logic [AXI_DATA_WIDTH-1:0] m_axi_wdata; + logic [AXI_STRB_WIDTH-1:0] m_axi_wstrb; + logic m_axi_wlast; + logic [AXI_USER_WIDTH-1:0] m_axi_wuser; + logic m_axi_wvalid; + logic m_axi_wready; + + logic [AXI_ID_WIDTH-1:0] m_axi_bid; + logic [1:0] m_axi_bresp; + logic [AXI_USER_WIDTH-1:0] m_axi_buser; + logic m_axi_bvalid; + logic m_axi_bready; + + logic [AXI_ID_WIDTH-1:0] m_axi_arid; + logic [AXI_ADDR_WIDTH-1:0] m_axi_araddr; + logic [7:0] m_axi_arlen; + logic [2:0] m_axi_arsize; + logic [1:0] m_axi_arburst; + logic m_axi_arlock; + logic [3:0] m_axi_arcache; + logic [2:0] m_axi_arprot; + logic [3:0] m_axi_arqos; + logic [3:0] m_axi_arregion; + logic [AXI_USER_WIDTH-1:0] m_axi_aruser; + logic m_axi_arvalid; + logic m_axi_arready; + + logic [AXI_ID_WIDTH-1:0] m_axi_rid; + logic [AXI_DATA_WIDTH-1:0] m_axi_rdata; + logic [1:0] m_axi_rresp; + logic m_axi_rlast; + logic [AXI_USER_WIDTH-1:0] m_axi_ruser; + logic m_axi_rvalid; + logic m_axi_rready; + + // Configuration visible to cocotb + logic read_enable; + logic write_enable; + logic write_abort; + + // -------------------------------------------------------------------------- + // Local interface instances + // -------------------------------------------------------------------------- + + axis_if #( + .DATA_W (AXIS_DATA_WIDTH), + .KEEP_W (AXIS_KEEP_WIDTH), + .ID_W (AXIS_ID_WIDTH), + .DEST_W (AXIS_DEST_WIDTH), + .USER_W (AXIS_USER_WIDTH) + ) m_axis_read_data_if ( + .aclk (clk), + .aresetn (rstn) + ); + + axis_if #( + .DATA_W (AXIS_DATA_WIDTH), + .KEEP_W (AXIS_KEEP_WIDTH), + .ID_W (AXIS_ID_WIDTH), + .DEST_W (AXIS_DEST_WIDTH), + .USER_W (AXIS_USER_WIDTH) + ) s_axis_write_data_if ( + .aclk (clk), + .aresetn (rstn) + ); + + axi4_if #( + .ADDR_W (AXI_ADDR_WIDTH), + .DATA_W (AXI_DATA_WIDTH), + .ID_W (AXI_ID_WIDTH), + .USER_W (AXI_USER_WIDTH) + ) m_axi_if ( + .aclk (clk), + .aresetn (rstn) + ); + + // cocotb flat write stream -> interface + axis_flat_to_if #( + .DATA_W (AXIS_DATA_WIDTH), + .KEEP_W (AXIS_KEEP_WIDTH), + .ID_W (AXIS_ID_WIDTH), + .DEST_W (AXIS_DEST_WIDTH), + .USER_W (AXIS_USER_WIDTH) + ) u_s_axis_write_data_flat_to_if ( + .s_axis_tdata (s_axis_write_data_tdata), + .s_axis_tkeep (s_axis_write_data_tkeep), + .s_axis_tstrb (s_axis_write_data_tstrb), + .s_axis_tlast (s_axis_write_data_tlast), + .s_axis_tid (s_axis_write_data_tid), + .s_axis_tdest (s_axis_write_data_tdest), + .s_axis_tuser (s_axis_write_data_tuser), + .s_axis_tvalid (s_axis_write_data_tvalid), + .s_axis_tready (s_axis_write_data_tready), + .m_axis (s_axis_write_data_if) + ); + + // wrapper read stream interface -> cocotb flat stream + axis_if_to_flat #( + .DATA_W (AXIS_DATA_WIDTH), + .KEEP_W (AXIS_KEEP_WIDTH), + .ID_W (AXIS_ID_WIDTH), + .DEST_W (AXIS_DEST_WIDTH), + .USER_W (AXIS_USER_WIDTH) + ) u_m_axis_read_data_if_to_flat ( + .s_axis (m_axis_read_data_if), + .m_axis_tdata (m_axis_read_data_tdata), + .m_axis_tkeep (m_axis_read_data_tkeep), + .m_axis_tstrb (m_axis_read_data_tstrb), + .m_axis_tlast (m_axis_read_data_tlast), + .m_axis_tid (m_axis_read_data_tid), + .m_axis_tdest (m_axis_read_data_tdest), + .m_axis_tuser (m_axis_read_data_tuser), + .m_axis_tvalid (m_axis_read_data_tvalid), + .m_axis_tready (m_axis_read_data_tready) + ); + + // wrapper AXI interface -> cocotb flat AXI memory bus + axi4_if_to_flat #( + .ADDR_W (AXI_ADDR_WIDTH), + .DATA_W (AXI_DATA_WIDTH), + .ID_W (AXI_ID_WIDTH), + .USER_W (AXI_USER_WIDTH) + ) u_m_axi_if_to_flat ( + .s_axi (m_axi_if), + + .m_axi_awid (m_axi_awid), + .m_axi_awaddr (m_axi_awaddr), + .m_axi_awlen (m_axi_awlen), + .m_axi_awsize (m_axi_awsize), + .m_axi_awburst (m_axi_awburst), + .m_axi_awlock (m_axi_awlock), + .m_axi_awcache (m_axi_awcache), + .m_axi_awprot (m_axi_awprot), + .m_axi_awqos (m_axi_awqos), + .m_axi_awregion (m_axi_awregion), + .m_axi_awuser (m_axi_awuser), + .m_axi_awvalid (m_axi_awvalid), + .m_axi_awready (m_axi_awready), + + .m_axi_wdata (m_axi_wdata), + .m_axi_wstrb (m_axi_wstrb), + .m_axi_wlast (m_axi_wlast), + .m_axi_wuser (m_axi_wuser), + .m_axi_wvalid (m_axi_wvalid), + .m_axi_wready (m_axi_wready), + + .m_axi_bid (m_axi_bid), + .m_axi_bresp (m_axi_bresp), + .m_axi_buser (m_axi_buser), + .m_axi_bvalid (m_axi_bvalid), + .m_axi_bready (m_axi_bready), + + .m_axi_arid (m_axi_arid), + .m_axi_araddr (m_axi_araddr), + .m_axi_arlen (m_axi_arlen), + .m_axi_arsize (m_axi_arsize), + .m_axi_arburst (m_axi_arburst), + .m_axi_arlock (m_axi_arlock), + .m_axi_arcache (m_axi_arcache), + .m_axi_arprot (m_axi_arprot), + .m_axi_arqos (m_axi_arqos), + .m_axi_arregion (m_axi_arregion), + .m_axi_aruser (m_axi_aruser), + .m_axi_arvalid (m_axi_arvalid), + .m_axi_arready (m_axi_arready), + + .m_axi_rid (m_axi_rid), + .m_axi_rdata (m_axi_rdata), + .m_axi_rresp (m_axi_rresp), + .m_axi_rlast (m_axi_rlast), + .m_axi_ruser (m_axi_ruser), + .m_axi_rvalid (m_axi_rvalid), + .m_axi_rready (m_axi_rready) + ); + + axi_dma_if_wrapper #( + .AXI_DATA_WIDTH (AXI_DATA_WIDTH), + .AXI_ADDR_WIDTH (AXI_ADDR_WIDTH), + .AXI_STRB_WIDTH (AXI_STRB_WIDTH), + .AXI_ID_WIDTH (AXI_ID_WIDTH), + .AXI_USER_WIDTH (AXI_USER_WIDTH), + .AXI_MAX_BURST_LEN (AXI_MAX_BURST_LEN), + .AXIS_DATA_WIDTH (AXIS_DATA_WIDTH), + .AXIS_KEEP_ENABLE (AXIS_KEEP_ENABLE), + .AXIS_KEEP_WIDTH (AXIS_KEEP_WIDTH), + .AXIS_LAST_ENABLE (AXIS_LAST_ENABLE), + .AXIS_ID_ENABLE (AXIS_ID_ENABLE), + .AXIS_ID_WIDTH (AXIS_ID_WIDTH), + .AXIS_DEST_ENABLE (AXIS_DEST_ENABLE), + .AXIS_DEST_WIDTH (AXIS_DEST_WIDTH), + .AXIS_USER_ENABLE (AXIS_USER_ENABLE), + .AXIS_USER_WIDTH (AXIS_USER_WIDTH), + .LEN_WIDTH (LEN_WIDTH), + .TAG_WIDTH (TAG_WIDTH), + .ENABLE_SG (ENABLE_SG), + .ENABLE_UNALIGNED (ENABLE_UNALIGNED) + ) u_dut ( + .clk (clk), + .rst (rst), + + .s_axis_read_desc_addr (s_axis_read_desc_addr), + .s_axis_read_desc_len (s_axis_read_desc_len), + .s_axis_read_desc_tag (s_axis_read_desc_tag), + .s_axis_read_desc_id (s_axis_read_desc_id), + .s_axis_read_desc_dest (s_axis_read_desc_dest), + .s_axis_read_desc_user (s_axis_read_desc_user), + .s_axis_read_desc_valid (s_axis_read_desc_valid), + .s_axis_read_desc_ready (s_axis_read_desc_ready), + + .m_axis_read_desc_status_tag (m_axis_read_desc_status_tag), + .m_axis_read_desc_status_error (m_axis_read_desc_status_error), + .m_axis_read_desc_status_valid (m_axis_read_desc_status_valid), + + .m_axis_read_data (m_axis_read_data_if), + + .s_axis_write_desc_addr (s_axis_write_desc_addr), + .s_axis_write_desc_len (s_axis_write_desc_len), + .s_axis_write_desc_tag (s_axis_write_desc_tag), + .s_axis_write_desc_valid (s_axis_write_desc_valid), + .s_axis_write_desc_ready (s_axis_write_desc_ready), + + .m_axis_write_desc_status_len (m_axis_write_desc_status_len), + .m_axis_write_desc_status_tag (m_axis_write_desc_status_tag), + .m_axis_write_desc_status_id (m_axis_write_desc_status_id), + .m_axis_write_desc_status_dest (m_axis_write_desc_status_dest), + .m_axis_write_desc_status_user (m_axis_write_desc_status_user), + .m_axis_write_desc_status_error (m_axis_write_desc_status_error), + .m_axis_write_desc_status_valid (m_axis_write_desc_status_valid), + + .s_axis_write_data (s_axis_write_data_if), + .m_axi (m_axi_if), + + .read_enable (read_enable), + .write_enable (write_enable), + .write_abort (write_abort) + ); + +endmodule : tb_axi_dma_wrapper + +`default_nettype wire