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refactor: move dma if converters to single file

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This commit is contained in:
Phil
2026-06-17 14:48:06 +03:00
parent 14004aa90e
commit da01c5856b
10 changed files with 194 additions and 222 deletions
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191
axi/rtl/axi_dma_if_wrapper.sv
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@ -8,6 +8,197 @@
`default_nettype none `default_nettype none
// DMA Specific wrappers & converters
module axi_dma_read_desc_flat_to_if #(
parameter int unsigned ADDR_W = 64,
parameter int unsigned LEN_W = 20,
parameter int unsigned TAG_W = 8,
parameter int unsigned ID_W = 8,
parameter int unsigned DEST_W = 8,
parameter int unsigned USER_W = 1
)(
input logic [ADDR_W-1:0] s_axis_read_desc_addr,
input logic [LEN_W-1:0] s_axis_read_desc_len,
input logic [TAG_W-1:0] s_axis_read_desc_tag,
input logic [ID_W-1:0] s_axis_read_desc_id,
input logic [DEST_W-1:0] s_axis_read_desc_dest,
input logic [USER_W-1:0] s_axis_read_desc_user,
input logic s_axis_read_desc_valid,
output logic s_axis_read_desc_ready,
axi_dma_read_desc_if.master m_axis_read_desc
);
assign m_axis_read_desc.req.addr = s_axis_read_desc_addr;
assign m_axis_read_desc.req.len = s_axis_read_desc_len;
assign m_axis_read_desc.req.tag = s_axis_read_desc_tag;
assign m_axis_read_desc.req.id = s_axis_read_desc_id;
assign m_axis_read_desc.req.dest = s_axis_read_desc_dest;
assign m_axis_read_desc.req.user = s_axis_read_desc_user;
assign m_axis_read_desc.req.valid = s_axis_read_desc_valid;
assign s_axis_read_desc_ready = m_axis_read_desc.resp.ready;
endmodule : axi_dma_read_desc_flat_to_if
module axi_dma_read_desc_if_to_flat #(
parameter int unsigned ADDR_W = 64,
parameter int unsigned LEN_W = 20,
parameter int unsigned TAG_W = 8,
parameter int unsigned ID_W = 8,
parameter int unsigned DEST_W = 8,
parameter int unsigned USER_W = 1
)(
axi_dma_read_desc_if.slave s_axis_read_desc,
output logic [ADDR_W-1:0] m_axis_read_desc_addr,
output logic [LEN_W-1:0] m_axis_read_desc_len,
output logic [TAG_W-1:0] m_axis_read_desc_tag,
output logic [ID_W-1:0] m_axis_read_desc_id,
output logic [DEST_W-1:0] m_axis_read_desc_dest,
output logic [USER_W-1:0] m_axis_read_desc_user,
output logic m_axis_read_desc_valid,
input logic m_axis_read_desc_ready
);
assign m_axis_read_desc_addr = s_axis_read_desc.req.addr;
assign m_axis_read_desc_len = s_axis_read_desc.req.len;
assign m_axis_read_desc_tag = s_axis_read_desc.req.tag;
assign m_axis_read_desc_id = s_axis_read_desc.req.id;
assign m_axis_read_desc_dest = s_axis_read_desc.req.dest;
assign m_axis_read_desc_user = s_axis_read_desc.req.user;
assign m_axis_read_desc_valid = s_axis_read_desc.req.valid;
assign s_axis_read_desc.resp.ready = m_axis_read_desc_ready;
endmodule : axi_dma_read_desc_if_to_flat
module axi_dma_read_desc_status_flat_to_if #(
parameter int unsigned TAG_W = 8
)(
input logic [TAG_W-1:0] m_axis_read_desc_status_tag,
input logic [3:0] m_axis_read_desc_status_error,
input logic m_axis_read_desc_status_valid,
axi_dma_read_desc_status_if.master m_axis_read_desc_status
);
assign m_axis_read_desc_status.req.tag = m_axis_read_desc_status_tag;
assign m_axis_read_desc_status.req.error = m_axis_read_desc_status_error;
assign m_axis_read_desc_status.req.valid = m_axis_read_desc_status_valid;
endmodule : axi_dma_read_desc_status_flat_to_if
module axi_dma_read_desc_status_if_to_flat #(
parameter int unsigned TAG_W = 8
)(
axi_dma_read_desc_status_if.slave s_axis_read_desc_status,
output logic [TAG_W-1:0] m_axis_read_desc_status_tag,
output logic [3:0] m_axis_read_desc_status_error,
output logic m_axis_read_desc_status_valid
);
assign m_axis_read_desc_status_tag = s_axis_read_desc_status.req.tag;
assign m_axis_read_desc_status_error = s_axis_read_desc_status.req.error;
assign m_axis_read_desc_status_valid = s_axis_read_desc_status.req.valid;
endmodule : axi_dma_read_desc_status_if_to_flat
module axi_dma_write_desc_flat_to_if #(
parameter int unsigned ADDR_W = 64,
parameter int unsigned LEN_W = 20,
parameter int unsigned TAG_W = 8
)(
input logic [ADDR_W-1:0] s_axis_write_desc_addr,
input logic [LEN_W-1:0] s_axis_write_desc_len,
input logic [TAG_W-1:0] s_axis_write_desc_tag,
input logic s_axis_write_desc_valid,
output logic s_axis_write_desc_ready,
axi_dma_write_desc_if.master m_axis_write_desc
);
assign m_axis_write_desc.req.addr = s_axis_write_desc_addr;
assign m_axis_write_desc.req.len = s_axis_write_desc_len;
assign m_axis_write_desc.req.tag = s_axis_write_desc_tag;
assign m_axis_write_desc.req.valid = s_axis_write_desc_valid;
assign s_axis_write_desc_ready = m_axis_write_desc.resp.ready;
endmodule : axi_dma_write_desc_flat_to_if
module axi_dma_write_desc_if_to_flat #(
parameter int unsigned ADDR_W = 64,
parameter int unsigned LEN_W = 20,
parameter int unsigned TAG_W = 8
)(
axi_dma_write_desc_if.slave s_axis_write_desc,
output logic [ADDR_W-1:0] m_axis_write_desc_addr,
output logic [LEN_W-1:0] m_axis_write_desc_len,
output logic [TAG_W-1:0] m_axis_write_desc_tag,
output logic m_axis_write_desc_valid,
input logic m_axis_write_desc_ready
);
assign m_axis_write_desc_addr = s_axis_write_desc.req.addr;
assign m_axis_write_desc_len = s_axis_write_desc.req.len;
assign m_axis_write_desc_tag = s_axis_write_desc.req.tag;
assign m_axis_write_desc_valid = s_axis_write_desc.req.valid;
assign s_axis_write_desc.resp.ready = m_axis_write_desc_ready;
endmodule : axi_dma_write_desc_if_to_flat
module axi_dma_write_desc_status_flat_to_if #(
parameter int unsigned LEN_W = 20,
parameter int unsigned TAG_W = 8,
parameter int unsigned ID_W = 8,
parameter int unsigned DEST_W = 8,
parameter int unsigned USER_W = 1
)(
input logic [LEN_W-1:0] m_axis_write_desc_status_len,
input logic [TAG_W-1:0] m_axis_write_desc_status_tag,
input logic [ID_W-1:0] m_axis_write_desc_status_id,
input logic [DEST_W-1:0] m_axis_write_desc_status_dest,
input logic [USER_W-1:0] m_axis_write_desc_status_user,
input logic [3:0] m_axis_write_desc_status_error,
input logic m_axis_write_desc_status_valid,
axi_dma_write_desc_status_if.master m_axis_write_desc_status
);
assign m_axis_write_desc_status.req.len = m_axis_write_desc_status_len;
assign m_axis_write_desc_status.req.tag = m_axis_write_desc_status_tag;
assign m_axis_write_desc_status.req.id = m_axis_write_desc_status_id;
assign m_axis_write_desc_status.req.dest = m_axis_write_desc_status_dest;
assign m_axis_write_desc_status.req.user = m_axis_write_desc_status_user;
assign m_axis_write_desc_status.req.error = m_axis_write_desc_status_error;
assign m_axis_write_desc_status.req.valid = m_axis_write_desc_status_valid;
endmodule : axi_dma_write_desc_status_flat_to_if
module axi_dma_write_desc_status_if_to_flat #(
parameter int unsigned LEN_W = 20,
parameter int unsigned TAG_W = 8,
parameter int unsigned ID_W = 8,
parameter int unsigned DEST_W = 8,
parameter int unsigned USER_W = 1
)(
axi_dma_write_desc_status_if.slave s_axis_write_desc_status,
output logic [LEN_W-1:0] m_axis_write_desc_status_len,
output logic [TAG_W-1:0] m_axis_write_desc_status_tag,
output logic [ID_W-1:0] m_axis_write_desc_status_id,
output logic [DEST_W-1:0] m_axis_write_desc_status_dest,
output logic [USER_W-1:0] m_axis_write_desc_status_user,
output logic [3:0] m_axis_write_desc_status_error,
output logic m_axis_write_desc_status_valid
);
assign m_axis_write_desc_status_len = s_axis_write_desc_status.req.len;
assign m_axis_write_desc_status_tag = s_axis_write_desc_status.req.tag;
assign m_axis_write_desc_status_id = s_axis_write_desc_status.req.id;
assign m_axis_write_desc_status_dest = s_axis_write_desc_status.req.dest;
assign m_axis_write_desc_status_user = s_axis_write_desc_status.req.user;
assign m_axis_write_desc_status_error = s_axis_write_desc_status.req.error;
assign m_axis_write_desc_status_valid = s_axis_write_desc_status.req.valid;
endmodule : axi_dma_write_desc_status_if_to_flat
module axi_dma_if_wrapper #( module axi_dma_if_wrapper #(
parameter int unsigned AXI_DATA_WIDTH = 32, parameter int unsigned AXI_DATA_WIDTH = 32,
parameter int unsigned AXI_ADDR_WIDTH = 16, parameter int unsigned AXI_ADDR_WIDTH = 16,

35
axi/rtl/axi_dma_read_desc_flat_to_if.sv
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@ -1,35 +0,0 @@
// SPDX-License-Identifier: MIT
`default_nettype none
module axi_dma_read_desc_flat_to_if #(
parameter int unsigned ADDR_W = 64,
parameter int unsigned LEN_W = 20,
parameter int unsigned TAG_W = 8,
parameter int unsigned ID_W = 8,
parameter int unsigned DEST_W = 8,
parameter int unsigned USER_W = 1
)(
input logic [ADDR_W-1:0] s_axis_read_desc_addr,
input logic [LEN_W-1:0] s_axis_read_desc_len,
input logic [TAG_W-1:0] s_axis_read_desc_tag,
input logic [ID_W-1:0] s_axis_read_desc_id,
input logic [DEST_W-1:0] s_axis_read_desc_dest,
input logic [USER_W-1:0] s_axis_read_desc_user,
input logic s_axis_read_desc_valid,
output logic s_axis_read_desc_ready,
axi_dma_read_desc_if.master m_axis_read_desc
);
assign m_axis_read_desc.req.addr = s_axis_read_desc_addr;
assign m_axis_read_desc.req.len = s_axis_read_desc_len;
assign m_axis_read_desc.req.tag = s_axis_read_desc_tag;
assign m_axis_read_desc.req.id = s_axis_read_desc_id;
assign m_axis_read_desc.req.dest = s_axis_read_desc_dest;
assign m_axis_read_desc.req.user = s_axis_read_desc_user;
assign m_axis_read_desc.req.valid = s_axis_read_desc_valid;
assign s_axis_read_desc_ready = m_axis_read_desc.resp.ready;
endmodule : axi_dma_read_desc_flat_to_if
`default_nettype wire

35
axi/rtl/axi_dma_read_desc_if_to_flat.sv
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@ -1,35 +0,0 @@
// SPDX-License-Identifier: MIT
`default_nettype none
module axi_dma_read_desc_if_to_flat #(
parameter int unsigned ADDR_W = 64,
parameter int unsigned LEN_W = 20,
parameter int unsigned TAG_W = 8,
parameter int unsigned ID_W = 8,
parameter int unsigned DEST_W = 8,
parameter int unsigned USER_W = 1
)(
axi_dma_read_desc_if.slave s_axis_read_desc,
output logic [ADDR_W-1:0] m_axis_read_desc_addr,
output logic [LEN_W-1:0] m_axis_read_desc_len,
output logic [TAG_W-1:0] m_axis_read_desc_tag,
output logic [ID_W-1:0] m_axis_read_desc_id,
output logic [DEST_W-1:0] m_axis_read_desc_dest,
output logic [USER_W-1:0] m_axis_read_desc_user,
output logic m_axis_read_desc_valid,
input logic m_axis_read_desc_ready
);
assign m_axis_read_desc_addr = s_axis_read_desc.req.addr;
assign m_axis_read_desc_len = s_axis_read_desc.req.len;
assign m_axis_read_desc_tag = s_axis_read_desc.req.tag;
assign m_axis_read_desc_id = s_axis_read_desc.req.id;
assign m_axis_read_desc_dest = s_axis_read_desc.req.dest;
assign m_axis_read_desc_user = s_axis_read_desc.req.user;
assign m_axis_read_desc_valid = s_axis_read_desc.req.valid;
assign s_axis_read_desc.resp.ready = m_axis_read_desc_ready;
endmodule : axi_dma_read_desc_if_to_flat
`default_nettype wire

19
axi/rtl/axi_dma_read_desc_status_flat_to_if.sv
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@ -1,19 +0,0 @@
// SPDX-License-Identifier: MIT
`default_nettype none
module axi_dma_read_desc_status_flat_to_if #(
parameter int unsigned TAG_W = 8
)(
input logic [TAG_W-1:0] m_axis_read_desc_status_tag,
input logic [3:0] m_axis_read_desc_status_error,
input logic m_axis_read_desc_status_valid,
axi_dma_read_desc_status_if.master m_axis_read_desc_status
);
assign m_axis_read_desc_status.req.tag = m_axis_read_desc_status_tag;
assign m_axis_read_desc_status.req.error = m_axis_read_desc_status_error;
assign m_axis_read_desc_status.req.valid = m_axis_read_desc_status_valid;
endmodule : axi_dma_read_desc_status_flat_to_if
`default_nettype wire

19
axi/rtl/axi_dma_read_desc_status_if_to_flat.sv
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@ -1,19 +0,0 @@
// SPDX-License-Identifier: MIT
`default_nettype none
module axi_dma_read_desc_status_if_to_flat #(
parameter int unsigned TAG_W = 8
)(
axi_dma_read_desc_status_if.slave s_axis_read_desc_status,
output logic [TAG_W-1:0] m_axis_read_desc_status_tag,
output logic [3:0] m_axis_read_desc_status_error,
output logic m_axis_read_desc_status_valid
);
assign m_axis_read_desc_status_tag = s_axis_read_desc_status.req.tag;
assign m_axis_read_desc_status_error = s_axis_read_desc_status.req.error;
assign m_axis_read_desc_status_valid = s_axis_read_desc_status.req.valid;
endmodule : axi_dma_read_desc_status_if_to_flat
`default_nettype wire

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axi/rtl/axi_dma_write_desc_flat_to_if.sv
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@ -1,26 +0,0 @@
// SPDX-License-Identifier: MIT
`default_nettype none
module axi_dma_write_desc_flat_to_if #(
parameter int unsigned ADDR_W = 64,
parameter int unsigned LEN_W = 20,
parameter int unsigned TAG_W = 8
)(
input logic [ADDR_W-1:0] s_axis_write_desc_addr,
input logic [LEN_W-1:0] s_axis_write_desc_len,
input logic [TAG_W-1:0] s_axis_write_desc_tag,
input logic s_axis_write_desc_valid,
output logic s_axis_write_desc_ready,
axi_dma_write_desc_if.master m_axis_write_desc
);
assign m_axis_write_desc.req.addr = s_axis_write_desc_addr;
assign m_axis_write_desc.req.len = s_axis_write_desc_len;
assign m_axis_write_desc.req.tag = s_axis_write_desc_tag;
assign m_axis_write_desc.req.valid = s_axis_write_desc_valid;
assign s_axis_write_desc_ready = m_axis_write_desc.resp.ready;
endmodule : axi_dma_write_desc_flat_to_if
`default_nettype wire

26
axi/rtl/axi_dma_write_desc_if_to_flat.sv
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@ -1,26 +0,0 @@
// SPDX-License-Identifier: MIT
`default_nettype none
module axi_dma_write_desc_if_to_flat #(
parameter int unsigned ADDR_W = 64,
parameter int unsigned LEN_W = 20,
parameter int unsigned TAG_W = 8
)(
axi_dma_write_desc_if.slave s_axis_write_desc,
output logic [ADDR_W-1:0] m_axis_write_desc_addr,
output logic [LEN_W-1:0] m_axis_write_desc_len,
output logic [TAG_W-1:0] m_axis_write_desc_tag,
output logic m_axis_write_desc_valid,
input logic m_axis_write_desc_ready
);
assign m_axis_write_desc_addr = s_axis_write_desc.req.addr;
assign m_axis_write_desc_len = s_axis_write_desc.req.len;
assign m_axis_write_desc_tag = s_axis_write_desc.req.tag;
assign m_axis_write_desc_valid = s_axis_write_desc.req.valid;
assign s_axis_write_desc.resp.ready = m_axis_write_desc_ready;
endmodule : axi_dma_write_desc_if_to_flat
`default_nettype wire

31
axi/rtl/axi_dma_write_desc_status_flat_to_if.sv
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@ -1,31 +0,0 @@
// SPDX-License-Identifier: MIT
`default_nettype none
module axi_dma_write_desc_status_flat_to_if #(
parameter int unsigned LEN_W = 20,
parameter int unsigned TAG_W = 8,
parameter int unsigned ID_W = 8,
parameter int unsigned DEST_W = 8,
parameter int unsigned USER_W = 1
)(
input logic [LEN_W-1:0] m_axis_write_desc_status_len,
input logic [TAG_W-1:0] m_axis_write_desc_status_tag,
input logic [ID_W-1:0] m_axis_write_desc_status_id,
input logic [DEST_W-1:0] m_axis_write_desc_status_dest,
input logic [USER_W-1:0] m_axis_write_desc_status_user,
input logic [3:0] m_axis_write_desc_status_error,
input logic m_axis_write_desc_status_valid,
axi_dma_write_desc_status_if.master m_axis_write_desc_status
);
assign m_axis_write_desc_status.req.len = m_axis_write_desc_status_len;
assign m_axis_write_desc_status.req.tag = m_axis_write_desc_status_tag;
assign m_axis_write_desc_status.req.id = m_axis_write_desc_status_id;
assign m_axis_write_desc_status.req.dest = m_axis_write_desc_status_dest;
assign m_axis_write_desc_status.req.user = m_axis_write_desc_status_user;
assign m_axis_write_desc_status.req.error = m_axis_write_desc_status_error;
assign m_axis_write_desc_status.req.valid = m_axis_write_desc_status_valid;
endmodule : axi_dma_write_desc_status_flat_to_if
`default_nettype wire

31
axi/rtl/axi_dma_write_desc_status_if_to_flat.sv
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@ -1,31 +0,0 @@
// SPDX-License-Identifier: MIT
`default_nettype none
module axi_dma_write_desc_status_if_to_flat #(
parameter int unsigned LEN_W = 20,
parameter int unsigned TAG_W = 8,
parameter int unsigned ID_W = 8,
parameter int unsigned DEST_W = 8,
parameter int unsigned USER_W = 1
)(
axi_dma_write_desc_status_if.slave s_axis_write_desc_status,
output logic [LEN_W-1:0] m_axis_write_desc_status_len,
output logic [TAG_W-1:0] m_axis_write_desc_status_tag,
output logic [ID_W-1:0] m_axis_write_desc_status_id,
output logic [DEST_W-1:0] m_axis_write_desc_status_dest,
output logic [USER_W-1:0] m_axis_write_desc_status_user,
output logic [3:0] m_axis_write_desc_status_error,
output logic m_axis_write_desc_status_valid
);
assign m_axis_write_desc_status_len = s_axis_write_desc_status.req.len;
assign m_axis_write_desc_status_tag = s_axis_write_desc_status.req.tag;
assign m_axis_write_desc_status_id = s_axis_write_desc_status.req.id;
assign m_axis_write_desc_status_dest = s_axis_write_desc_status.req.dest;
assign m_axis_write_desc_status_user = s_axis_write_desc_status.req.user;
assign m_axis_write_desc_status_error = s_axis_write_desc_status.req.error;
assign m_axis_write_desc_status_valid = s_axis_write_desc_status.req.valid;
endmodule : axi_dma_write_desc_status_if_to_flat
`default_nettype wire

3
axi/tb/axi_dma_wrapper/Makefile
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@ -36,6 +36,9 @@ VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axi4_if_to_flat.sv
VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axis_flat_to_if.sv VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axis_flat_to_if.sv
VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axis_if_to_flat.sv VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axis_if_to_flat.sv
VERILOG_SOURCES += $(AXI_IF_RTL_DIR)/axi_dma_desc_if.sv
VERILOG_SOURCES += $(FORENCICH_AXI_RTL_DIR)/axi_dma.v VERILOG_SOURCES += $(FORENCICH_AXI_RTL_DIR)/axi_dma.v
VERILOG_SOURCES += $(FORENCICH_AXI_RTL_DIR)/axi_dma_rd.v VERILOG_SOURCES += $(FORENCICH_AXI_RTL_DIR)/axi_dma_rd.v
VERILOG_SOURCES += $(FORENCICH_AXI_RTL_DIR)/axi_dma_wr.v VERILOG_SOURCES += $(FORENCICH_AXI_RTL_DIR)/axi_dma_wr.v