diff --git a/axi/tb/axi_cocotb_loopback_test/tb_axi4_loopback.sv b/axi/tb/axi_cocotb_loopback_test/tb_axi4_loopback.sv new file mode 100644 index 0000000..9bcd721 --- /dev/null +++ b/axi/tb/axi_cocotb_loopback_test/tb_axi4_loopback.sv @@ -0,0 +1,252 @@ +`timescale 1ns/1ps + +module tb_axi4_loopback #( + parameter int unsigned ADDR_W = 32, + parameter int unsigned DATA_W = 64, + parameter int unsigned ID_W = 4, + parameter int unsigned USER_W = 1 +)( + input logic clk, + input logic rst, + + // slave-side flat AXI port (cocotb driven) + input logic [ID_W-1:0] s_axi_awid, + input logic [ADDR_W-1:0] s_axi_awaddr, + input logic [7:0] s_axi_awlen, + input logic [2:0] s_axi_awsize, + input logic [1:0] s_axi_awburst, + input logic s_axi_awlock, + input logic [3:0] s_axi_awcache, + input logic [2:0] s_axi_awprot, + input logic [3:0] s_axi_awqos, + input logic [3:0] s_axi_awregion, + input logic [USER_W-1:0] s_axi_awuser, + input logic s_axi_awvalid, + output logic s_axi_awready, + + input logic [DATA_W-1:0] s_axi_wdata, + input logic [DATA_W/8-1:0] s_axi_wstrb, + input logic s_axi_wlast, + input logic [USER_W-1:0] s_axi_wuser, + input logic s_axi_wvalid, + output logic s_axi_wready, + + output logic [ID_W-1:0] s_axi_bid, + output logic [1:0] s_axi_bresp, + output logic [USER_W-1:0] s_axi_buser, + output logic s_axi_bvalid, + input logic s_axi_bready, + + input logic [ID_W-1:0] s_axi_arid, + input logic [ADDR_W-1:0] s_axi_araddr, + input logic [7:0] s_axi_arlen, + input logic [2:0] s_axi_arsize, + input logic [1:0] s_axi_arburst, + input logic s_axi_arlock, + input logic [3:0] s_axi_arcache, + input logic [2:0] s_axi_arprot, + input logic [3:0] s_axi_arqos, + input logic [3:0] s_axi_arregion, + input logic [USER_W-1:0] s_axi_aruser, + input logic s_axi_arvalid, + output logic s_axi_arready, + + output logic [ID_W-1:0] s_axi_rid, + output logic [DATA_W-1:0] s_axi_rdata, + output logic [1:0] s_axi_rresp, + output logic s_axi_rlast, + output logic [USER_W-1:0] s_axi_ruser, + output logic s_axi_rvalid, + input logic s_axi_rready, + + // master-side flat AXI port for coco-tb + output logic [ID_W-1:0] m_axi_awid, + output logic [ADDR_W-1:0] m_axi_awaddr, + output logic [7:0] m_axi_awlen, + output logic [2:0] m_axi_awsize, + output logic [1:0] m_axi_awburst, + output logic m_axi_awlock, + output logic [3:0] m_axi_awcache, + output logic [2:0] m_axi_awprot, + output logic [3:0] m_axi_awqos, + output logic [3:0] m_axi_awregion, + output logic [USER_W-1:0] m_axi_awuser, + output logic m_axi_awvalid, + input logic m_axi_awready, + + output logic [DATA_W-1:0] m_axi_wdata, + output logic [DATA_W/8-1:0] m_axi_wstrb, + output logic m_axi_wlast, + output logic [USER_W-1:0] m_axi_wuser, + output logic m_axi_wvalid, + input logic m_axi_wready, + + input logic [ID_W-1:0] m_axi_bid, + input logic [1:0] m_axi_bresp, + input logic [USER_W-1:0] m_axi_buser, + input logic m_axi_bvalid, + output logic m_axi_bready, + + output logic [ID_W-1:0] m_axi_arid, + output logic [ADDR_W-1:0] m_axi_araddr, + output logic [7:0] m_axi_arlen, + output logic [2:0] m_axi_arsize, + output logic [1:0] m_axi_arburst, + output logic m_axi_arlock, + output logic [3:0] m_axi_arcache, + output logic [2:0] m_axi_arprot, + output logic [3:0] m_axi_arqos, + output logic [3:0] m_axi_arregion, + output logic [USER_W-1:0] m_axi_aruser, + output logic m_axi_arvalid, + input logic m_axi_arready, + + input logic [ID_W-1:0] m_axi_rid, + input logic [DATA_W-1:0] m_axi_rdata, + input logic [1:0] m_axi_rresp, + input logic m_axi_rlast, + input logic [USER_W-1:0] m_axi_ruser, + input logic m_axi_rvalid, + output logic m_axi_rready +); + + logic aresetn; + assign aresetn = ~rst; + + axi4_if #( + .ADDR_W(ADDR_W), + .DATA_W(DATA_W), + .ID_W(ID_W), + .USER_W(USER_W) + ) axi_in ( + .aclk(clk), + .aresetn(aresetn) + ); + + axi4_if #( + .ADDR_W(ADDR_W), + .DATA_W(DATA_W), + .ID_W(ID_W), + .USER_W(USER_W) + ) axi_out ( + .aclk(clk), + .aresetn(aresetn) + ); + + axi4_flat_to_if #( + .ADDR_W(ADDR_W), + .DATA_W(DATA_W), + .ID_W(ID_W), + .USER_W(USER_W) + ) u_flat_to_if ( + .s_axi_awid (s_axi_awid), + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awlen (s_axi_awlen), + .s_axi_awsize (s_axi_awsize), + .s_axi_awburst (s_axi_awburst), + .s_axi_awlock (s_axi_awlock), + .s_axi_awcache (s_axi_awcache), + .s_axi_awprot (s_axi_awprot), + .s_axi_awqos (s_axi_awqos), + .s_axi_awregion (s_axi_awregion), + .s_axi_awuser (s_axi_awuser), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awready (s_axi_awready), + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_wlast (s_axi_wlast), + .s_axi_wuser (s_axi_wuser), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wready (s_axi_wready), + .s_axi_bid (s_axi_bid), + .s_axi_bresp (s_axi_bresp), + .s_axi_buser (s_axi_buser), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bready (s_axi_bready), + .s_axi_arid (s_axi_arid), + .s_axi_araddr (s_axi_araddr), + .s_axi_arlen (s_axi_arlen), + .s_axi_arsize (s_axi_arsize), + .s_axi_arburst (s_axi_arburst), + .s_axi_arlock (s_axi_arlock), + .s_axi_arcache (s_axi_arcache), + .s_axi_arprot (s_axi_arprot), + .s_axi_arqos (s_axi_arqos), + .s_axi_arregion (s_axi_arregion), + .s_axi_aruser (s_axi_aruser), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_arready (s_axi_arready), + .s_axi_rid (s_axi_rid), + .s_axi_rdata (s_axi_rdata), + .s_axi_rresp (s_axi_rresp), + .s_axi_rlast (s_axi_rlast), + .s_axi_ruser (s_axi_ruser), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rready (s_axi_rready), + .m_axi (axi_in) + ); + + axi4_loopback #( + .ADDR_W(ADDR_W), + .DATA_W(DATA_W), + .ID_W(ID_W), + .USER_W(USER_W) + ) dut ( + .s_axi(axi_in), + .m_axi(axi_out) + ); + + axi4_if_to_flat #( + .ADDR_W(ADDR_W), + .DATA_W(DATA_W), + .ID_W(ID_W), + .USER_W(USER_W) + ) u_if_to_flat ( + .s_axi (axi_out), + .m_axi_awid (m_axi_awid), + .m_axi_awaddr (m_axi_awaddr), + .m_axi_awlen (m_axi_awlen), + .m_axi_awsize (m_axi_awsize), + .m_axi_awburst (m_axi_awburst), + .m_axi_awlock (m_axi_awlock), + .m_axi_awcache (m_axi_awcache), + .m_axi_awprot (m_axi_awprot), + .m_axi_awqos (m_axi_awqos), + .m_axi_awregion (m_axi_awregion), + .m_axi_awuser (m_axi_awuser), + .m_axi_awvalid (m_axi_awvalid), + .m_axi_awready (m_axi_awready), + .m_axi_wdata (m_axi_wdata), + .m_axi_wstrb (m_axi_wstrb), + .m_axi_wlast (m_axi_wlast), + .m_axi_wuser (m_axi_wuser), + .m_axi_wvalid (m_axi_wvalid), + .m_axi_wready (m_axi_wready), + .m_axi_bid (m_axi_bid), + .m_axi_bresp (m_axi_bresp), + .m_axi_buser (m_axi_buser), + .m_axi_bvalid (m_axi_bvalid), + .m_axi_bready (m_axi_bready), + .m_axi_arid (m_axi_arid), + .m_axi_araddr (m_axi_araddr), + .m_axi_arlen (m_axi_arlen), + .m_axi_arsize (m_axi_arsize), + .m_axi_arburst (m_axi_arburst), + .m_axi_arlock (m_axi_arlock), + .m_axi_arcache (m_axi_arcache), + .m_axi_arprot (m_axi_arprot), + .m_axi_arqos (m_axi_arqos), + .m_axi_arregion (m_axi_arregion), + .m_axi_aruser (m_axi_aruser), + .m_axi_arvalid (m_axi_arvalid), + .m_axi_arready (m_axi_arready), + .m_axi_rid (m_axi_rid), + .m_axi_rdata (m_axi_rdata), + .m_axi_rresp (m_axi_rresp), + .m_axi_rlast (m_axi_rlast), + .m_axi_ruser (m_axi_ruser), + .m_axi_rvalid (m_axi_rvalid), + .m_axi_rready (m_axi_rready) + ); + +endmodule