From 3261b66aaa0900095003800c5f387bcbae8b1c19 Mon Sep 17 00:00:00 2001 From: Phil Date: Fri, 29 May 2026 15:30:24 +0300 Subject: [PATCH 1/2] fix: syntax errors --- axi/axi_crossbar_wrapper.sv | 2 +- axi/axi_if.sv | 4 ++-- axi/axil_cdc_wrapper.sv | 8 ++++---- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/axi/axi_crossbar_wrapper.sv b/axi/axi_crossbar_wrapper.sv index 25adeac..c3212bd 100644 --- a/axi/axi_crossbar_wrapper.sv +++ b/axi/axi_crossbar_wrapper.sv @@ -2,7 +2,7 @@ module axi_crossbar_wrapper #( parameter int SLAVE_QTY = 3, parameter int MASTER_QTY = 3, parameter int ADDR_WIDTH = 32, - parameter int DATA_WIDTH = 32 + parameter int DATA_WIDTH = 32, parameter int STRB_WIDTH = (DATA_WIDTH/8) )( input wire clk, diff --git a/axi/axi_if.sv b/axi/axi_if.sv index 66af213..af8cb7e 100644 --- a/axi/axi_if.sv +++ b/axi/axi_if.sv @@ -13,7 +13,7 @@ interface axi4_if #( typedef logic [DATA_W/8-1:0] strb_t; typedef logic [ID_W-1:0] id_t; typedef logic [USER_W-1:0] user_t; - `AXI4_TYPEDEF_ALL(axi, addr_t, data_t, strb_t, id_t, user_t) + `AXI4_TYPEDEF_ALL(axi, addr_t, data_t, strb_t, id_t, user_t); axi_req_t req; axi_resp_t resp; modport master (input aclk, aresetn, output req, input resp); @@ -34,7 +34,7 @@ interface axi4l_if #( typedef logic [DATA_W-1:0] data_t; typedef logic [DATA_W/8-1:0] strb_t; typedef logic [USER_W-1:0] user_t; - `AXI4L_TYPEDEF_ALL(axil, addr_t, data_t, strb_t, user_t) + `AXI4L_TYPEDEF_ALL(axil, addr_t, data_t, strb_t, user_t); axil_req_t req; axil_resp_t resp; modport master (input aclk, aresetn, output req, input resp); diff --git a/axi/axil_cdc_wrapper.sv b/axi/axil_cdc_wrapper.sv index 09a547c..e6012c9 100644 --- a/axi/axil_cdc_wrapper.sv +++ b/axi/axil_cdc_wrapper.sv @@ -1,6 +1,6 @@ module axil_cdc_wrapper #( - parameter int ADDR_WIDTH = 32 - parameter int DATA_WIDTH = 32, + parameter int ADDR_WIDTH = 32, + parameter int DATA_WIDTH = 32 )( input wire s_clk, input wire s_rst, @@ -83,8 +83,8 @@ module axil_cdc_wrapper #( ); axil_cdc #( - .ADDR_WIDTH (ADDR_WIDTH) - .DATA_WIDTH (DATA_WIDTH), + .ADDR_WIDTH (ADDR_WIDTH), + .DATA_WIDTH (DATA_WIDTH) ) i_axil_cdc ( .s_clk (s_clk), .s_rst (s_rst), From 2c96a8758515e8d637163ce712666b80a36979f5 Mon Sep 17 00:00:00 2001 From: Phil Date: Fri, 29 May 2026 15:30:42 +0300 Subject: [PATCH 2/2] fix: experimental change to fix reg map pkg for vivado --- axi/axi_reg/dma_axil_reg_map_pkg.sv | 75 ++++++++++++++++++++--------- 1 file changed, 51 insertions(+), 24 deletions(-) diff --git a/axi/axi_reg/dma_axil_reg_map_pkg.sv b/axi/axi_reg/dma_axil_reg_map_pkg.sv index 554d74d..09b5b38 100644 --- a/axi/axi_reg/dma_axil_reg_map_pkg.sv +++ b/axi/axi_reg/dma_axil_reg_map_pkg.sv @@ -1,37 +1,64 @@ package dma_axil_reg_map_pkg; - localparam int unsigned DMA_AXIL_REG_MAP_N_REGS = 4; + localparam int unsigned DMA_AXIL_REG_MAP_N_REGS = 6; + + localparam int unsigned DMA_WRITE_DESC_CONTROL_REG = 0; + localparam int unsigned DMA_WRITE_DESC_ADDR_REG = 1; + localparam int unsigned DMA_WRITE_DESC_LEN_REG = 2; + localparam int unsigned DMA_READ_DESC_CONTROL_REG = 3; + localparam int unsigned DMA_READ_DESC_ADDR_REG = 4; + localparam int unsigned DMA_READ_DESC_LEN_REG = 5; localparam logic [2:0] REG_BIT_RSVD = 3'd0; localparam logic [2:0] REG_BIT_RO = 3'd1; localparam logic [2:0] REG_BIT_RW = 3'd2; localparam logic [2:0] REG_BIT_W1S = 3'd3; - localparam logic [2:0] REG_BIT_W1C = 3'd4; - localparam DMA_WRITE_DESC_CONTROL_REG = 0; - localparam DMA_WRITE_DESC_ADDR_REG = 1; - localparam DMA_WRITE_DESC_LEN_REG = 2; - localparam DMA_READ_DESC_CONTROL_REG = 3; - localparam DMA_READ_DESC_ADDR_REG = 4; - localparam DMA_READ_DESC_LEN_REG = 5; + typedef logic [DMA_AXIL_REG_MAP_N_REGS-1:0][31:0][2:0] reg_mode_map_t; - localparam logic [DMA_AXIL_REG_MAP_N_REGS-1:0][31:0][2:0] DMA_AXIL_REG_MAP_REG_MODE = '{ + function automatic reg_mode_map_t make_dma_reg_mode(); + reg_mode_map_t mode; - '{REG_BIT_RO, REG_BIT_W1S, default: REG_BIT_RSVD}, - '{32{REG_BIT_RW}, default: REG_BIT_RSVD}, - '{32{REG_BIT_RW}, default: REG_BIT_RSVD}, - '{REG_BIT_RO, REG_BIT_W1S, default: REG_BIT_RSVD}, - '{32{REG_BIT_RW}, default: REG_BIT_RSVD}, - '{32{REG_BIT_RW}, default: REG_BIT_RSVD} - }; + mode = '0; - localparam logic [DMA_AXIL_REG_MAP_N_REGS-1:0][31:0] DMA_AXIL_REG_MAP_REG_RST = '{ - 32'h0000_0000, - 32'h0000_0000, - 32'h0000_0000, - 32'h0000_0000, - 32'h0000_0000, - 32'h0000_0000 - }; + // По умолчанию всё reserved + for (int reg_idx = 0; reg_idx < DMA_AXIL_REG_MAP_N_REGS; reg_idx++) begin + for (int bit_idx = 0; bit_idx < 32; bit_idx++) begin + mode[reg_idx][bit_idx] = REG_BIT_RSVD; + end + end + + // WRITE CONTROL + mode[DMA_WRITE_DESC_CONTROL_REG][0] = REG_BIT_RO; + mode[DMA_WRITE_DESC_CONTROL_REG][1] = REG_BIT_W1S; + + // WRITE ADDR + for (int bit_idx = 0; bit_idx < 32; bit_idx++) begin + mode[DMA_WRITE_DESC_ADDR_REG][bit_idx] = REG_BIT_RW; + end + + // WRITE LEN + for (int bit_idx = 0; bit_idx < 32; bit_idx++) begin + mode[DMA_WRITE_DESC_LEN_REG][bit_idx] = REG_BIT_RW; + end + + // READ CONTROL + mode[DMA_READ_DESC_CONTROL_REG][0] = REG_BIT_RO; + mode[DMA_READ_DESC_CONTROL_REG][1] = REG_BIT_W1S; + + // READ ADDR + for (int bit_idx = 0; bit_idx < 32; bit_idx++) begin + mode[DMA_READ_DESC_ADDR_REG][bit_idx] = REG_BIT_RW; + end + + // READ LEN + for (int bit_idx = 0; bit_idx < 32; bit_idx++) begin + mode[DMA_READ_DESC_LEN_REG][bit_idx] = REG_BIT_RW; + end + + return mode; + endfunction + + localparam reg_mode_map_t DMA_AXIL_REG_MAP_REG_MODE = make_dma_reg_mode(); endpackage \ No newline at end of file