diff --git a/axi/tb/axil_reg_cocotb/Makefile b/axi/tb/axil_reg_cocotb/Makefile
new file mode 100644
index 0000000..3798194
--- /dev/null
+++ b/axi/tb/axil_reg_cocotb/Makefile
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: MIT
+
+TOPLEVEL_LANG = verilog
+SIM ?= verilator
+
+PWD := $(shell pwd)
+
+# Directory with axi_pkg.sv, axi_if.sv and axi4l_reg_map.sv.
+# Override it from command line if your tree is different:
+#   make SIM=verilator RTL_DIR=/path/to/rtl_libs/axi
+RTL_DIR ?= $(PWD)/../../../axi
+TB_DIR  ?= $(PWD)
+
+TOPLEVEL = tb_axi4l_reg_map
+MODULE   = test_axi4l_reg_map
+
+export PYTHONPATH := $(TB_DIR):$(PYTHONPATH)
+
+VERILOG_SOURCES += $(RTL_DIR)/rtl/axi_pkg.sv
+VERILOG_SOURCES += $(RTL_DIR)/rtl/axi_if.sv
+VERILOG_SOURCES += $(RTL_DIR)/axi_reg/axi4l_reg_map.sv
+VERILOG_SOURCES += $(TB_DIR)/tb_axi4l_reg_map.sv
+
+COMPILE_ARGS += -I$(RTL_DIR)
+
+ifeq ($(SIM),verilator)
+EXTRA_ARGS += --trace
+EXTRA_ARGS += --trace-structs
+EXTRA_ARGS += --public-flat-rw
+EXTRA_ARGS += -Wno-fatal
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim