From 7bafa8534f1c73a76592d345d2680ff7a1a29987 Mon Sep 17 00:00:00 2001 From: Phil Date: Thu, 11 Jun 2026 15:47:59 +0300 Subject: [PATCH] rtl: add write desc converters --- axi/rtl/axi_dma_write_desc_flat_to_if.sv | 26 ++++++++++++++++ axi/rtl/axi_dma_write_desc_if_to_flat.sv | 26 ++++++++++++++++ .../axi_dma_write_desc_status_flat_to_if.sv | 31 +++++++++++++++++++ .../axi_dma_write_desc_status_if_to_flat.sv | 31 +++++++++++++++++++ 4 files changed, 114 insertions(+) create mode 100644 axi/rtl/axi_dma_write_desc_flat_to_if.sv create mode 100644 axi/rtl/axi_dma_write_desc_if_to_flat.sv create mode 100644 axi/rtl/axi_dma_write_desc_status_flat_to_if.sv create mode 100644 axi/rtl/axi_dma_write_desc_status_if_to_flat.sv diff --git a/axi/rtl/axi_dma_write_desc_flat_to_if.sv b/axi/rtl/axi_dma_write_desc_flat_to_if.sv new file mode 100644 index 0000000..24a6b2a --- /dev/null +++ b/axi/rtl/axi_dma_write_desc_flat_to_if.sv @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: MIT + +`default_nettype none + +module axi_dma_write_desc_flat_to_if #( + parameter int unsigned ADDR_W = 64, + parameter int unsigned LEN_W = 20, + parameter int unsigned TAG_W = 8 +)( + input logic [ADDR_W-1:0] s_axis_write_desc_addr, + input logic [LEN_W-1:0] s_axis_write_desc_len, + input logic [TAG_W-1:0] s_axis_write_desc_tag, + input logic s_axis_write_desc_valid, + output logic s_axis_write_desc_ready, + + axi_dma_write_desc_if.master m_axis_write_desc +); + assign m_axis_write_desc.req.addr = s_axis_write_desc_addr; + assign m_axis_write_desc.req.len = s_axis_write_desc_len; + assign m_axis_write_desc.req.tag = s_axis_write_desc_tag; + assign m_axis_write_desc.req.valid = s_axis_write_desc_valid; + + assign s_axis_write_desc_ready = m_axis_write_desc.resp.ready; +endmodule : axi_dma_write_desc_flat_to_if + +`default_nettype wire diff --git a/axi/rtl/axi_dma_write_desc_if_to_flat.sv b/axi/rtl/axi_dma_write_desc_if_to_flat.sv new file mode 100644 index 0000000..d6d1c5d --- /dev/null +++ b/axi/rtl/axi_dma_write_desc_if_to_flat.sv @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: MIT + +`default_nettype none + +module axi_dma_write_desc_if_to_flat #( + parameter int unsigned ADDR_W = 64, + parameter int unsigned LEN_W = 20, + parameter int unsigned TAG_W = 8 +)( + axi_dma_write_desc_if.slave s_axis_write_desc, + + output logic [ADDR_W-1:0] m_axis_write_desc_addr, + output logic [LEN_W-1:0] m_axis_write_desc_len, + output logic [TAG_W-1:0] m_axis_write_desc_tag, + output logic m_axis_write_desc_valid, + input logic m_axis_write_desc_ready +); + assign m_axis_write_desc_addr = s_axis_write_desc.req.addr; + assign m_axis_write_desc_len = s_axis_write_desc.req.len; + assign m_axis_write_desc_tag = s_axis_write_desc.req.tag; + assign m_axis_write_desc_valid = s_axis_write_desc.req.valid; + + assign s_axis_write_desc.resp.ready = m_axis_write_desc_ready; +endmodule : axi_dma_write_desc_if_to_flat + +`default_nettype wire diff --git a/axi/rtl/axi_dma_write_desc_status_flat_to_if.sv b/axi/rtl/axi_dma_write_desc_status_flat_to_if.sv new file mode 100644 index 0000000..52f7da6 --- /dev/null +++ b/axi/rtl/axi_dma_write_desc_status_flat_to_if.sv @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: MIT + +`default_nettype none + +module axi_dma_write_desc_status_flat_to_if #( + parameter int unsigned LEN_W = 20, + parameter int unsigned TAG_W = 8, + parameter int unsigned ID_W = 8, + parameter int unsigned DEST_W = 8, + parameter int unsigned USER_W = 1 +)( + input logic [LEN_W-1:0] m_axis_write_desc_status_len, + input logic [TAG_W-1:0] m_axis_write_desc_status_tag, + input logic [ID_W-1:0] m_axis_write_desc_status_id, + input logic [DEST_W-1:0] m_axis_write_desc_status_dest, + input logic [USER_W-1:0] m_axis_write_desc_status_user, + input logic [3:0] m_axis_write_desc_status_error, + input logic m_axis_write_desc_status_valid, + + axi_dma_write_desc_status_if.master m_axis_write_desc_status +); + assign m_axis_write_desc_status.req.len = m_axis_write_desc_status_len; + assign m_axis_write_desc_status.req.tag = m_axis_write_desc_status_tag; + assign m_axis_write_desc_status.req.id = m_axis_write_desc_status_id; + assign m_axis_write_desc_status.req.dest = m_axis_write_desc_status_dest; + assign m_axis_write_desc_status.req.user = m_axis_write_desc_status_user; + assign m_axis_write_desc_status.req.error = m_axis_write_desc_status_error; + assign m_axis_write_desc_status.req.valid = m_axis_write_desc_status_valid; +endmodule : axi_dma_write_desc_status_flat_to_if + +`default_nettype wire diff --git a/axi/rtl/axi_dma_write_desc_status_if_to_flat.sv b/axi/rtl/axi_dma_write_desc_status_if_to_flat.sv new file mode 100644 index 0000000..88e41d6 --- /dev/null +++ b/axi/rtl/axi_dma_write_desc_status_if_to_flat.sv @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: MIT + +`default_nettype none + +module axi_dma_write_desc_status_if_to_flat #( + parameter int unsigned LEN_W = 20, + parameter int unsigned TAG_W = 8, + parameter int unsigned ID_W = 8, + parameter int unsigned DEST_W = 8, + parameter int unsigned USER_W = 1 +)( + axi_dma_write_desc_status_if.slave s_axis_write_desc_status, + + output logic [LEN_W-1:0] m_axis_write_desc_status_len, + output logic [TAG_W-1:0] m_axis_write_desc_status_tag, + output logic [ID_W-1:0] m_axis_write_desc_status_id, + output logic [DEST_W-1:0] m_axis_write_desc_status_dest, + output logic [USER_W-1:0] m_axis_write_desc_status_user, + output logic [3:0] m_axis_write_desc_status_error, + output logic m_axis_write_desc_status_valid +); + assign m_axis_write_desc_status_len = s_axis_write_desc_status.req.len; + assign m_axis_write_desc_status_tag = s_axis_write_desc_status.req.tag; + assign m_axis_write_desc_status_id = s_axis_write_desc_status.req.id; + assign m_axis_write_desc_status_dest = s_axis_write_desc_status.req.dest; + assign m_axis_write_desc_status_user = s_axis_write_desc_status.req.user; + assign m_axis_write_desc_status_error = s_axis_write_desc_status.req.error; + assign m_axis_write_desc_status_valid = s_axis_write_desc_status.req.valid; +endmodule : axi_dma_write_desc_status_if_to_flat + +`default_nettype wire