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fix: axi4l reg example update

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This commit is contained in:
Phil
2026-06-17 18:09:13 +03:00
parent 4a4c8d8ef2
commit 51956ffd2d
2 changed files with 91 additions and 51 deletions
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35
axi/axi_reg/axi4l_reg_map_example.sv
View File

@ -8,8 +8,14 @@ module axi4l_reg_map_example #(
axi4l_if.slave s_axil,
output logic start_o,
output logic soft_reset_o,
output logic enable_o,
output logic irq_enable_o,
output logic [31:0] config_o,
input logic busy_i,
input logic done_i,
input logic error_i,
input logic [7:0] error_code_i
);
import axi4l_reg_map_example_pkg::*;
@ -39,22 +45,23 @@ module axi4l_reg_map_example #(
always_comb begin
reg_i = '0;
// REG1 @ 0x04: status register
// bit 0 : busy (RO)
reg_i[1][0] = busy_i;
// REG_STATUS @ 0x04
reg_i[REG_STATUS][STATUS_BUSY_BIT] = busy_i;
reg_i[REG_STATUS][STATUS_DONE_BIT] = done_i;
reg_i[REG_STATUS][STATUS_ERROR_BIT] = error_i;
reg_i[REG_STATUS][STATUS_ERROR_CODE_MSB:STATUS_ERROR_CODE_LSB] = error_code_i;
// REG2 @ 0x08: error register
// bits 7:0: error_code (RO)
reg_i[2][7:0] = error_code_i;
// REG_VERSION @ 0x0c
reg_i[REG_VERSION] = VERSION_VAL;
end
// REG0 @ 0x00: control register
// bit 0 : start (W1S pulse)
// bit 1 : enable (RW)
assign start_o = reg_pulse[0][0];
assign enable_o = reg_o[0][1];
// REG_CTRL @ 0x00
assign start_o = reg_pulse[REG_CTRL][CTRL_START_BIT];
assign soft_reset_o = reg_pulse[REG_CTRL][CTRL_SOFT_RESET_BIT];
assign enable_o = reg_o[REG_CTRL][CTRL_ENABLE_BIT];
assign irq_enable_o = reg_o[REG_CTRL][CTRL_IRQ_ENABLE_BIT];
// REG3 @ 0x0C: generic configuration register (RW)
// reg_o[3] can be manually connected later if needed.
// REG_CONFIG @ 0x08
assign config_o = reg_o[REG_CONFIG];
endmodule
endmodule : axi4l_reg_map_example

71
axi/axi_reg/axi4l_reg_map_example_pkg.sv
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@ -1,35 +1,68 @@
package axi4l_reg_map_example_pkg;
import axi4l_reg_map_pkg::*;
localparam int unsigned AXI4L_REG_MAP_EXAMPLE_N_REGS = 4;
localparam logic [2:0] REG_BIT_RSVD = 3'd0;
localparam logic [2:0] REG_BIT_RO = 3'd1;
localparam logic [2:0] REG_BIT_RW = 3'd2;
localparam logic [2:0] REG_BIT_W1S = 3'd3;
localparam int unsigned REG_CTRL = 0;
localparam int unsigned REG_STATUS = 1;
localparam int unsigned REG_CONFIG = 2;
localparam int unsigned REG_VERSION = 3;
localparam logic [15:0] REG_CTRL_ADDR = 16'h0000;
localparam logic [15:0] REG_STATUS_ADDR = 16'h0004;
localparam logic [15:0] REG_CONFIG_ADDR = 16'h0008;
localparam logic [15:0] REG_VERSION_ADDR = 16'h000c;
localparam int unsigned CTRL_START_BIT = 0;
localparam int unsigned CTRL_SOFT_RESET_BIT = 1;
localparam int unsigned CTRL_ENABLE_BIT = 2;
localparam int unsigned CTRL_IRQ_ENABLE_BIT = 3;
localparam int unsigned STATUS_BUSY_BIT = 0;
localparam int unsigned STATUS_DONE_BIT = 1;
localparam int unsigned STATUS_ERROR_BIT = 2;
localparam int unsigned STATUS_ERROR_CODE_LSB = 8;
localparam int unsigned STATUS_ERROR_CODE_MSB = 15;
localparam logic [31:0] CONFIG_RST = 32'h0000_0001;
localparam logic [31:0] VERSION_VAL = 32'h0001_0000;
localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0][2:0] AXI4L_REG_MAP_EXAMPLE_REG_MODE = '{
'{
REG_BIT_W1S,
REG_BIT_RW,
REG_CTRL: '{
CTRL_START_BIT : REG_BIT_W1S,
CTRL_SOFT_RESET_BIT : REG_BIT_W1S,
CTRL_ENABLE_BIT : REG_BIT_RW,
CTRL_IRQ_ENABLE_BIT : REG_BIT_RW,
default : REG_BIT_RSVD
},
'{
REG_BIT_RO,
REG_STATUS: '{
STATUS_BUSY_BIT : REG_BIT_RO,
STATUS_DONE_BIT : REG_BIT_RO,
STATUS_ERROR_BIT : REG_BIT_RO,
STATUS_ERROR_CODE_LSB : REG_BIT_RO,
STATUS_ERROR_CODE_LSB+1 : REG_BIT_RO,
STATUS_ERROR_CODE_LSB+2 : REG_BIT_RO,
STATUS_ERROR_CODE_LSB+3 : REG_BIT_RO,
STATUS_ERROR_CODE_LSB+4 : REG_BIT_RO,
STATUS_ERROR_CODE_LSB+5 : REG_BIT_RO,
STATUS_ERROR_CODE_LSB+6 : REG_BIT_RO,
STATUS_ERROR_CODE_LSB+7 : REG_BIT_RO,
default : REG_BIT_RSVD
},
'{
REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO,
REG_BIT_RO, REG_BIT_RO, REG_BIT_RO, REG_BIT_RO,
default: REG_BIT_RSVD
REG_CONFIG: '{
default: REG_BIT_RW
},
'{default: REG_BIT_RW}
REG_VERSION: '{
default: REG_BIT_RO
}
};
localparam logic [AXI4L_REG_MAP_EXAMPLE_N_REGS-1:0][31:0] AXI4L_REG_MAP_EXAMPLE_REG_RST = '{
32'h0000_0000,
32'h0000_0000,
32'h0000_0000,
32'h0000_0001
REG_CTRL : 32'h0000_0000,
REG_STATUS : 32'h0000_0000,
REG_CONFIG : CONFIG_RST,
REG_VERSION : 32'h0000_0000
};
endpackage
endpackage : axi4l_reg_map_example_pkg