rtl: add axiS dma wrapper & tests
This commit is contained in:
Phil
345
axi/rtl/axi_dma_compat.sv
Normal file
345
axi/rtl/axi_dma_compat.sv
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// SPDX-License-Identifier: MIT
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//
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// Compatibility wrapper over axi_dma_if_wrapper.
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//
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// Uses 4 axis_if channels for statuses and descs
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//
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// payload packing is LSB-first and one descriptor/status occupies one AXIS beat.
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// tkeep/tstrb/tlast/id/dest/user on descriptor inputs are ignored.
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// status outputs drive tkeep/tstrb to all ones, tlast to 1, and id/dest/user to 0.
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//
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// !!!!!: the original alexforencich axi_dma status outputs have
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// no ready/backpressure signal. This wrapper adds a oneentry holding register
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// for each status axis output, but if a downstream is not ready long enough for a
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// second status to arrive while the first one is still pending, the core cannot
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// be backpressured. In normal use keep status sinks ready, or add an external
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// FIFO if long stalls are possible.
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`default_nettype none
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module axi_dma_axis_compat #(
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parameter int unsigned AXI_DATA_WIDTH = 32,
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parameter int unsigned AXI_ADDR_WIDTH = 16,
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parameter int unsigned AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8,
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parameter int unsigned AXI_ID_WIDTH = 8,
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parameter int unsigned AXI_USER_WIDTH = 1,
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parameter int unsigned AXI_MAX_BURST_LEN = 16,
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parameter int unsigned AXIS_DATA_WIDTH = AXI_DATA_WIDTH,
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parameter int unsigned AXIS_KEEP_ENABLE = AXIS_DATA_WIDTH > 8,
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parameter int unsigned AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH / 8,
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parameter int unsigned AXIS_LAST_ENABLE = 1,
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parameter int unsigned AXIS_ID_ENABLE = 1,
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parameter int unsigned AXIS_ID_WIDTH = 8,
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parameter int unsigned AXIS_DEST_ENABLE = 0,
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parameter int unsigned AXIS_DEST_WIDTH = 8,
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parameter int unsigned AXIS_USER_ENABLE = 1,
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parameter int unsigned AXIS_USER_WIDTH = 1,
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parameter int unsigned LEN_WIDTH = 20,
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parameter int unsigned TAG_WIDTH = 8,
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parameter int unsigned ENABLE_SG = 0,
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parameter int unsigned ENABLE_UNALIGNED = 0,
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// Payload widths for descriptor/status AXIS streams.
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parameter int unsigned READ_DESC_PAYLOAD_WIDTH = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH,
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parameter int unsigned READ_DESC_AXIS_DATA_WIDTH = ((READ_DESC_PAYLOAD_WIDTH + 7) / 8) * 8,
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parameter int unsigned READ_DESC_STATUS_PAYLOAD_WIDTH = TAG_WIDTH + 4,
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parameter int unsigned READ_DESC_STATUS_AXIS_DATA_WIDTH = ((READ_DESC_STATUS_PAYLOAD_WIDTH + 7) / 8) * 8,
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parameter int unsigned WRITE_DESC_PAYLOAD_WIDTH = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH,
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parameter int unsigned WRITE_DESC_AXIS_DATA_WIDTH = ((WRITE_DESC_PAYLOAD_WIDTH + 7) / 8) * 8,
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parameter int unsigned WRITE_DESC_STATUS_PAYLOAD_WIDTH = LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH + 4,
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parameter int unsigned WRITE_DESC_STATUS_AXIS_DATA_WIDTH = ((WRITE_DESC_STATUS_PAYLOAD_WIDTH + 7) / 8) * 8
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)(
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input logic clk,
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input logic rst,
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/*
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* AXI read descriptor input, encoded as one AXIS beat.
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* tdata layout, LSB first:
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* addr | len | tag | id | dest | user
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*/
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axis_if.slave s_axis_read_desc,
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/*
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* AXI read descriptor status output, encoded as one AXIS beat.
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* tdata layout, LSB first:
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* tag | error
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*/
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axis_if.master m_axis_read_desc_status,
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/*
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* AXI stream read data output.
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*/
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axis_if.master m_axis_read_data,
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/*
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* AXI write descriptor input, encoded as one AXIS beat.
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* tdata layout, LSB first:
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* addr | len | tag
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*/
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axis_if.slave s_axis_write_desc,
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/*
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* AXI write descriptor status output, encoded as one AXIS beat.
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* tdata layout, LSB first:
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* len | tag | id | dest | user | error
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*/
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axis_if.master m_axis_write_desc_status,
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/*
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* AXI stream write data input.
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*/
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axis_if.slave s_axis_write_data,
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/*
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* AXI memory master interface.
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*/
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axi4_if.master m_axi,
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/*
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* Configuration.
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*/
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input logic read_enable,
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input logic write_enable,
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input logic write_abort
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);
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localparam int unsigned RD_ADDR_LSB = 0;
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localparam int unsigned RD_LEN_LSB = RD_ADDR_LSB + AXI_ADDR_WIDTH;
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localparam int unsigned RD_TAG_LSB = RD_LEN_LSB + LEN_WIDTH;
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localparam int unsigned RD_ID_LSB = RD_TAG_LSB + TAG_WIDTH;
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localparam int unsigned RD_DEST_LSB = RD_ID_LSB + AXIS_ID_WIDTH;
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localparam int unsigned RD_USER_LSB = RD_DEST_LSB + AXIS_DEST_WIDTH;
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localparam int unsigned RDS_TAG_LSB = 0;
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localparam int unsigned RDS_ERROR_LSB = RDS_TAG_LSB + TAG_WIDTH;
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localparam int unsigned WD_ADDR_LSB = 0;
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localparam int unsigned WD_LEN_LSB = WD_ADDR_LSB + AXI_ADDR_WIDTH;
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localparam int unsigned WD_TAG_LSB = WD_LEN_LSB + LEN_WIDTH;
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localparam int unsigned WDS_LEN_LSB = 0;
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localparam int unsigned WDS_TAG_LSB = WDS_LEN_LSB + LEN_WIDTH;
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localparam int unsigned WDS_ID_LSB = WDS_TAG_LSB + TAG_WIDTH;
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localparam int unsigned WDS_DEST_LSB = WDS_ID_LSB + AXIS_ID_WIDTH;
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localparam int unsigned WDS_USER_LSB = WDS_DEST_LSB + AXIS_DEST_WIDTH;
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localparam int unsigned WDS_ERROR_LSB = WDS_USER_LSB + AXIS_USER_WIDTH;
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localparam int unsigned READ_DESC_AXIS_KEEP_WIDTH = READ_DESC_AXIS_DATA_WIDTH / 8;
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localparam int unsigned READ_DESC_STATUS_AXIS_KEEP_WIDTH = READ_DESC_STATUS_AXIS_DATA_WIDTH / 8;
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localparam int unsigned WRITE_DESC_AXIS_KEEP_WIDTH = WRITE_DESC_AXIS_DATA_WIDTH / 8;
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localparam int unsigned WRITE_DESC_STATUS_AXIS_KEEP_WIDTH = WRITE_DESC_STATUS_AXIS_DATA_WIDTH / 8;
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logic rstn;
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assign rstn = ~rst;
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// --------------------------------------------------------------------------
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// Internal DMA-specific descriptor/status interfaces expected by
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// axi_dma_if_wrapper.
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// --------------------------------------------------------------------------
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axi_dma_read_desc_if #(
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.ADDR_W (AXI_ADDR_WIDTH),
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.LEN_W (LEN_WIDTH),
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.TAG_W (TAG_WIDTH),
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.ID_W (AXIS_ID_WIDTH),
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.DEST_W (AXIS_DEST_WIDTH),
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.USER_W (AXIS_USER_WIDTH)
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) read_desc_if (
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.aclk (clk),
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.aresetn (rstn)
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);
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axi_dma_read_desc_status_if #(
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.TAG_W (TAG_WIDTH)
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) read_desc_status_if (
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.aclk (clk),
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.aresetn (rstn)
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);
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axi_dma_write_desc_if #(
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.ADDR_W (AXI_ADDR_WIDTH),
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.LEN_W (LEN_WIDTH),
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.TAG_W (TAG_WIDTH)
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) write_desc_if (
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.aclk (clk),
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.aresetn (rstn)
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);
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axi_dma_write_desc_status_if #(
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.LEN_W (LEN_WIDTH),
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.TAG_W (TAG_WIDTH),
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.ID_W (AXIS_ID_WIDTH),
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.DEST_W (AXIS_DEST_WIDTH),
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.USER_W (AXIS_USER_WIDTH)
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) write_desc_status_if (
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.aclk (clk),
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.aresetn (rstn)
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);
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// --------------------------------------------------------------------------
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// AXIS read descriptor input -> DMA-specific read descriptor interface.
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// --------------------------------------------------------------------------
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assign read_desc_if.req.addr = s_axis_read_desc.req.t.data[RD_ADDR_LSB +: AXI_ADDR_WIDTH];
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assign read_desc_if.req.len = s_axis_read_desc.req.t.data[RD_LEN_LSB +: LEN_WIDTH];
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assign read_desc_if.req.tag = s_axis_read_desc.req.t.data[RD_TAG_LSB +: TAG_WIDTH];
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assign read_desc_if.req.id = s_axis_read_desc.req.t.data[RD_ID_LSB +: AXIS_ID_WIDTH];
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assign read_desc_if.req.dest = s_axis_read_desc.req.t.data[RD_DEST_LSB +: AXIS_DEST_WIDTH];
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assign read_desc_if.req.user = s_axis_read_desc.req.t.data[RD_USER_LSB +: AXIS_USER_WIDTH];
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assign read_desc_if.req.valid = s_axis_read_desc.req.t.valid;
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assign s_axis_read_desc.resp.ready = read_desc_if.resp.ready;
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// --------------------------------------------------------------------------
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// AXIS write descriptor input -> DMA-specific write descriptor interface.
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// --------------------------------------------------------------------------
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assign write_desc_if.req.addr = s_axis_write_desc.req.t.data[WD_ADDR_LSB +: AXI_ADDR_WIDTH];
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assign write_desc_if.req.len = s_axis_write_desc.req.t.data[WD_LEN_LSB +: LEN_WIDTH];
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assign write_desc_if.req.tag = s_axis_write_desc.req.t.data[WD_TAG_LSB +: TAG_WIDTH];
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assign write_desc_if.req.valid = s_axis_write_desc.req.t.valid;
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assign s_axis_write_desc.resp.ready = write_desc_if.resp.ready;
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// --------------------------------------------------------------------------
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// DMA-specific read status -> AXIS read status output.
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// --------------------------------------------------------------------------
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logic [READ_DESC_STATUS_AXIS_DATA_WIDTH-1:0] read_status_payload;
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logic [READ_DESC_STATUS_AXIS_DATA_WIDTH-1:0] read_status_data_q;
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logic read_status_valid_q;
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always_comb begin
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read_status_payload = '0;
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read_status_payload[RDS_TAG_LSB +: TAG_WIDTH] = read_desc_status_if.req.tag;
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read_status_payload[RDS_ERROR_LSB +: 4] = read_desc_status_if.req.error;
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end
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always_ff @(posedge clk) begin
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if (rst) begin
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read_status_valid_q <= 1'b0;
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read_status_data_q <= '0;
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end else begin
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if (!read_status_valid_q || m_axis_read_desc_status.resp.ready) begin
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read_status_valid_q <= read_desc_status_if.req.valid;
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if (read_desc_status_if.req.valid) begin
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read_status_data_q <= read_status_payload;
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end else begin
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read_status_data_q <= '0;
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end
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end
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end
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end
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always_comb begin
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m_axis_read_desc_status.req.t.data = '0;
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m_axis_read_desc_status.req.t.keep = '0;
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m_axis_read_desc_status.req.t.strb = '0;
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m_axis_read_desc_status.req.t.last = read_status_valid_q;
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m_axis_read_desc_status.req.t.id = '0;
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m_axis_read_desc_status.req.t.dest = '0;
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m_axis_read_desc_status.req.t.user = '0;
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m_axis_read_desc_status.req.t.valid = read_status_valid_q;
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m_axis_read_desc_status.req.t.data[READ_DESC_STATUS_AXIS_DATA_WIDTH-1:0] = read_status_data_q;
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m_axis_read_desc_status.req.t.keep[READ_DESC_STATUS_AXIS_KEEP_WIDTH-1:0] = {READ_DESC_STATUS_AXIS_KEEP_WIDTH{read_status_valid_q}};
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m_axis_read_desc_status.req.t.strb[READ_DESC_STATUS_AXIS_KEEP_WIDTH-1:0] = {READ_DESC_STATUS_AXIS_KEEP_WIDTH{read_status_valid_q}};
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end
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// --------------------------------------------------------------------------
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// DMA-specific write status -> AXIS write status output.
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// --------------------------------------------------------------------------
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logic [WRITE_DESC_STATUS_AXIS_DATA_WIDTH-1:0] write_status_payload;
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logic [WRITE_DESC_STATUS_AXIS_DATA_WIDTH-1:0] write_status_data_q;
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logic write_status_valid_q;
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always_comb begin
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write_status_payload = '0;
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write_status_payload[WDS_LEN_LSB +: LEN_WIDTH] = write_desc_status_if.req.len;
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write_status_payload[WDS_TAG_LSB +: TAG_WIDTH] = write_desc_status_if.req.tag;
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write_status_payload[WDS_ID_LSB +: AXIS_ID_WIDTH] = write_desc_status_if.req.id;
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write_status_payload[WDS_DEST_LSB +: AXIS_DEST_WIDTH] = write_desc_status_if.req.dest;
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write_status_payload[WDS_USER_LSB +: AXIS_USER_WIDTH] = write_desc_status_if.req.user;
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write_status_payload[WDS_ERROR_LSB +: 4] = write_desc_status_if.req.error;
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end
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always_ff @(posedge clk) begin
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if (rst) begin
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write_status_valid_q <= 1'b0;
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write_status_data_q <= '0;
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end else begin
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if (!write_status_valid_q || m_axis_write_desc_status.resp.ready) begin
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write_status_valid_q <= write_desc_status_if.req.valid;
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if (write_desc_status_if.req.valid) begin
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write_status_data_q <= write_status_payload;
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end else begin
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write_status_data_q <= '0;
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end
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end
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end
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end
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always_comb begin
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m_axis_write_desc_status.req.t.data = '0;
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m_axis_write_desc_status.req.t.keep = '0;
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m_axis_write_desc_status.req.t.strb = '0;
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m_axis_write_desc_status.req.t.last = write_status_valid_q;
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m_axis_write_desc_status.req.t.id = '0;
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m_axis_write_desc_status.req.t.dest = '0;
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m_axis_write_desc_status.req.t.user = '0;
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m_axis_write_desc_status.req.t.valid = write_status_valid_q;
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m_axis_write_desc_status.req.t.data[WRITE_DESC_STATUS_AXIS_DATA_WIDTH-1:0] = write_status_data_q;
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m_axis_write_desc_status.req.t.keep[WRITE_DESC_STATUS_AXIS_KEEP_WIDTH-1:0] = {WRITE_DESC_STATUS_AXIS_KEEP_WIDTH{write_status_valid_q}};
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m_axis_write_desc_status.req.t.strb[WRITE_DESC_STATUS_AXIS_KEEP_WIDTH-1:0] = {WRITE_DESC_STATUS_AXIS_KEEP_WIDTH{write_status_valid_q}};
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end
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// --------------------------------------------------------------------------
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// Lower-level wrapper: DMA-specific descriptor/status interfaces inside,
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// ordinary AXIS data and AXI memory interfaces unchanged.
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// --------------------------------------------------------------------------
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axi_dma_if_wrapper #(
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.AXI_DATA_WIDTH (AXI_DATA_WIDTH),
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.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
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.AXI_STRB_WIDTH (AXI_STRB_WIDTH),
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.AXI_ID_WIDTH (AXI_ID_WIDTH),
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.AXI_USER_WIDTH (AXI_USER_WIDTH),
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.AXI_MAX_BURST_LEN (AXI_MAX_BURST_LEN),
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.AXIS_DATA_WIDTH (AXIS_DATA_WIDTH),
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.AXIS_KEEP_ENABLE (AXIS_KEEP_ENABLE),
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.AXIS_KEEP_WIDTH (AXIS_KEEP_WIDTH),
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.AXIS_LAST_ENABLE (AXIS_LAST_ENABLE),
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.AXIS_ID_ENABLE (AXIS_ID_ENABLE),
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.AXIS_ID_WIDTH (AXIS_ID_WIDTH),
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.AXIS_DEST_ENABLE (AXIS_DEST_ENABLE),
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.AXIS_DEST_WIDTH (AXIS_DEST_WIDTH),
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.AXIS_USER_ENABLE (AXIS_USER_ENABLE),
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.AXIS_USER_WIDTH (AXIS_USER_WIDTH),
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.LEN_WIDTH (LEN_WIDTH),
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.TAG_WIDTH (TAG_WIDTH),
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.ENABLE_SG (ENABLE_SG),
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.ENABLE_UNALIGNED (ENABLE_UNALIGNED)
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) u_axi_dma_if_wrapper (
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.clk (clk),
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.rst (rst),
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.s_axis_read_desc (read_desc_if),
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.m_axis_read_desc_status (read_desc_status_if),
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.m_axis_read_data (m_axis_read_data),
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.s_axis_write_desc (write_desc_if),
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.m_axis_write_desc_status (write_desc_status_if),
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.s_axis_write_data (s_axis_write_data),
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.m_axi (m_axi),
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.read_enable (read_enable),
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.write_enable (write_enable),
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.write_abort (write_abort)
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);
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endmodule : axi_dma_axis_compat
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`default_nettype wire
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