diff --git a/axi/tb/axi_dma_wrapper/test_axi_dma_wrapper.py b/axi/tb/axi_dma_wrapper/test_axi_dma_wrapper.py
index 014f89f..c43ac9d 100644
--- a/axi/tb/axi_dma_wrapper/test_axi_dma_wrapper.py
+++ b/axi/tb/axi_dma_wrapper/test_axi_dma_wrapper.py
@@ -302,6 +302,9 @@ if pytest is not None:
         axi_if_rtl_dir = os.environ.get(
             "AXI_IF_RTL_DIR", os.path.join(project_root, "rtl", "axi")
         )
+        dma_if_rtl_dir = os.environ.get(
+            "DMA_IF_RTL_DIR", os.path.join(project_root, "rtl", "dma")
+        )
         wrapper_rtl_dir = os.environ.get(
             "WRAPPER_RTL_DIR", os.path.join(project_root, "rtl", "wrappers")
         )
@@ -346,6 +349,19 @@ if pytest is not None:
             os.path.join(axi_if_rtl_dir, "axi4_if_to_flat.sv"),
             os.path.join(axi_if_rtl_dir, "axis_flat_to_if.sv"),
             os.path.join(axi_if_rtl_dir, "axis_if_to_flat.sv"),
+            os.path.join(dma_if_rtl_dir, "axi_dma_desc_if.sv"),
+            os.path.join(dma_if_rtl_dir, "axi_dma_read_desc_flat_to_if.sv"),
+            os.path.join(dma_if_rtl_dir, "axi_dma_read_desc_if_to_flat.sv"),
+            os.path.join(dma_if_rtl_dir,
+                         "axi_dma_read_desc_status_flat_to_if.sv"),
+            os.path.join(dma_if_rtl_dir,
+                         "axi_dma_read_desc_status_if_to_flat.sv"),
+            os.path.join(dma_if_rtl_dir, "axi_dma_write_desc_flat_to_if.sv"),
+            os.path.join(dma_if_rtl_dir, "axi_dma_write_desc_if_to_flat.sv"),
+            os.path.join(dma_if_rtl_dir,
+                         "axi_dma_write_desc_status_flat_to_if.sv"),
+            os.path.join(dma_if_rtl_dir,
+                         "axi_dma_write_desc_status_if_to_flat.sv"),
             os.path.join(forencich_rtl_dir, "axi_dma.v"),
             os.path.join(forencich_rtl_dir, "axi_dma_rd.v"),
             os.path.join(forencich_rtl_dir, "axi_dma_wr.v"),
@@ -364,7 +380,8 @@ if pytest is not None:
         cocotb_test.simulator.run(
             python_search=[tests_dir],
             verilog_sources=verilog_sources,
-            includes=[axi_if_rtl_dir, wrapper_rtl_dir, forencich_rtl_dir],
+            includes=[axi_if_rtl_dir, dma_if_rtl_dir,
+                      wrapper_rtl_dir, forencich_rtl_dir],
             toplevel=toplevel,
             module=module,
             parameters=parameters,