rtl: add axi dma if collection

axi/rtl/axi_dma_desc_if.sv

@@ -0,0 +1,109 @@
+`default_nettype none
+
+interface axi_dma_read_desc_if #(
+  parameter int unsigned ADDR_W = 64,
+  parameter int unsigned LEN_W  = 20,
+  parameter int unsigned TAG_W  = 8,
+  parameter int unsigned ID_W   = 8,
+  parameter int unsigned DEST_W = 8,
+  parameter int unsigned USER_W = 1
+)(
+  input logic aclk,
+  input logic aresetn
+);
+  typedef struct packed {
+    logic [ADDR_W-1:0] addr;
+    logic [LEN_W-1:0]  len;
+    logic [TAG_W-1:0]  tag;
+    logic [ID_W-1:0]   id;
+    logic [DEST_W-1:0] dest;
+    logic [USER_W-1:0] user;
+    logic              valid;
+  } req_t;
+
+  typedef struct packed {
+    logic ready;
+  } resp_t;
+
+  req_t  req;
+  resp_t resp;
+
+  modport master  (input aclk, aresetn, output req, input  resp);
+  modport slave   (input aclk, aresetn, input  req, output resp);
+  modport monitor (input aclk, aresetn, input  req, input  resp);
+endinterface : axi_dma_read_desc_if
+
+interface axi_dma_read_desc_status_if #(
+  parameter int unsigned TAG_W = 8
+)(
+  input logic aclk,
+  input logic aresetn
+);
+  typedef struct packed {
+    logic [TAG_W-1:0] tag;
+    logic [3:0]       error;
+    logic             valid;
+  } req_t;
+
+  req_t req;
+
+  modport master  (input aclk, aresetn, output req);
+  modport slave   (input aclk, aresetn, input  req);
+  modport monitor (input aclk, aresetn, input  req);
+endinterface : axi_dma_read_desc_status_if
+
+interface axi_dma_write_desc_if #(
+  parameter int unsigned ADDR_W = 64,
+  parameter int unsigned LEN_W  = 20,
+  parameter int unsigned TAG_W  = 8
+)(
+  input logic aclk,
+  input logic aresetn
+);
+  typedef struct packed {
+    logic [ADDR_W-1:0] addr;
+    logic [LEN_W-1:0]  len;
+    logic [TAG_W-1:0]  tag;
+    logic              valid;
+  } req_t;
+
+  typedef struct packed {
+    logic ready;
+  } resp_t;
+
+  req_t  req;
+  resp_t resp;
+
+  modport master  (input aclk, aresetn, output req, input  resp);
+  modport slave   (input aclk, aresetn, input  req, output resp);
+  modport monitor (input aclk, aresetn, input  req, input  resp);
+endinterface : axi_dma_write_desc_if
+
+interface axi_dma_write_desc_status_if #(
+  parameter int unsigned LEN_W  = 20,
+  parameter int unsigned TAG_W  = 8,
+  parameter int unsigned ID_W   = 8,
+  parameter int unsigned DEST_W = 8,
+  parameter int unsigned USER_W = 1
+)(
+  input logic aclk,
+  input logic aresetn
+);
+  typedef struct packed {
+    logic [LEN_W-1:0]  len;
+    logic [TAG_W-1:0]  tag;
+    logic [ID_W-1:0]   id;
+    logic [DEST_W-1:0] dest;
+    logic [USER_W-1:0] user;
+    logic [3:0]        error;
+    logic              valid;
+  } req_t;
+
+  req_t req;
+
+  modport master  (input aclk, aresetn, output req);
+  modport slave   (input aclk, aresetn, input  req);
+  modport monitor (input aclk, aresetn, input  req);
+endinterface : axi_dma_write_desc_status_if
+
+`default_nettype wire