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rtl: re-factor dma for new ifaces

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Phil
2026-06-11 17:03:37 +03:00
parent 7bafa8534f
commit 0933768537
1 changed files with 124 additions and 56 deletions
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180
axi/rtl/axi_dma_if_wrapper.sv
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@ -1,12 +1,10 @@
// SPDX-License-Identifier: MIT
//
// Thin SystemVerilog interface wrapper around alexforencich/verilog-axi axi_dma.v.
// SystemVerilog interface wrapper around alexforencich/verilog-axi axi_dma.v.
//
// Policy used here:
// * AXI memory master is exposed as axi4_if.master.
// * AXI-Stream read/write data paths are exposed as axis_if master/slave.
// * Descriptor and status channels remain flat because they are DMA-specific
// command/status streams, not generic AXI-Stream data interfaces.
// AXI memory, AXI-Stream data, DMA descriptor, and DMA status channels are all
// exposed through compact interfaces. The original Forencich core remains
// untouched and is connected through local flat wires.
`default_nettype none
@ -38,23 +36,14 @@ module axi_dma_if_wrapper #(
input logic rst,
/*
* AXI read descriptor input, kept flat intentionally.
* AXI read descriptor input.
*/
input logic [AXI_ADDR_WIDTH-1:0] s_axis_read_desc_addr,
input logic [LEN_WIDTH-1:0] s_axis_read_desc_len,
input logic [TAG_WIDTH-1:0] s_axis_read_desc_tag,
input logic [AXIS_ID_WIDTH-1:0] s_axis_read_desc_id,
input logic [AXIS_DEST_WIDTH-1:0] s_axis_read_desc_dest,
input logic [AXIS_USER_WIDTH-1:0] s_axis_read_desc_user,
input logic s_axis_read_desc_valid,
output logic s_axis_read_desc_ready,
axi_dma_read_desc_if.slave s_axis_read_desc,
/*
* AXI read descriptor status output, kept flat intentionally.
* AXI read descriptor status output.
*/
output logic [TAG_WIDTH-1:0] m_axis_read_desc_status_tag,
output logic [3:0] m_axis_read_desc_status_error,
output logic m_axis_read_desc_status_valid,
axi_dma_read_desc_status_if.master m_axis_read_desc_status,
/*
* AXI stream read data output.
@ -62,24 +51,14 @@ module axi_dma_if_wrapper #(
axis_if.master m_axis_read_data,
/*
* AXI write descriptor input, kept flat intentionally.
* AXI write descriptor input.
*/
input logic [AXI_ADDR_WIDTH-1:0] s_axis_write_desc_addr,
input logic [LEN_WIDTH-1:0] s_axis_write_desc_len,
input logic [TAG_WIDTH-1:0] s_axis_write_desc_tag,
input logic s_axis_write_desc_valid,
output logic s_axis_write_desc_ready,
axi_dma_write_desc_if.slave s_axis_write_desc,
/*
* AXI write descriptor status output, kept flat intentionally.
* AXI write descriptor status output.
*/
output logic [LEN_WIDTH-1:0] m_axis_write_desc_status_len,
output logic [TAG_WIDTH-1:0] m_axis_write_desc_status_tag,
output logic [AXIS_ID_WIDTH-1:0] m_axis_write_desc_status_id,
output logic [AXIS_DEST_WIDTH-1:0] m_axis_write_desc_status_dest,
output logic [AXIS_USER_WIDTH-1:0] m_axis_write_desc_status_user,
output logic [3:0] m_axis_write_desc_status_error,
output logic m_axis_write_desc_status_valid,
axi_dma_write_desc_status_if.master m_axis_write_desc_status,
/*
* AXI stream write data input.
@ -103,6 +82,33 @@ module axi_dma_if_wrapper #(
// Flat wires connected to original alexforencich axi_dma.v
// --------------------------------------------------------------------------
logic [AXI_ADDR_WIDTH-1:0] dma_s_axis_read_desc_addr;
logic [LEN_WIDTH-1:0] dma_s_axis_read_desc_len;
logic [TAG_WIDTH-1:0] dma_s_axis_read_desc_tag;
logic [AXIS_ID_WIDTH-1:0] dma_s_axis_read_desc_id;
logic [AXIS_DEST_WIDTH-1:0] dma_s_axis_read_desc_dest;
logic [AXIS_USER_WIDTH-1:0] dma_s_axis_read_desc_user;
logic dma_s_axis_read_desc_valid;
logic dma_s_axis_read_desc_ready;
logic [TAG_WIDTH-1:0] dma_m_axis_read_desc_status_tag;
logic [3:0] dma_m_axis_read_desc_status_error;
logic dma_m_axis_read_desc_status_valid;
logic [AXI_ADDR_WIDTH-1:0] dma_s_axis_write_desc_addr;
logic [LEN_WIDTH-1:0] dma_s_axis_write_desc_len;
logic [TAG_WIDTH-1:0] dma_s_axis_write_desc_tag;
logic dma_s_axis_write_desc_valid;
logic dma_s_axis_write_desc_ready;
logic [LEN_WIDTH-1:0] dma_m_axis_write_desc_status_len;
logic [TAG_WIDTH-1:0] dma_m_axis_write_desc_status_tag;
logic [AXIS_ID_WIDTH-1:0] dma_m_axis_write_desc_status_id;
logic [AXIS_DEST_WIDTH-1:0] dma_m_axis_write_desc_status_dest;
logic [AXIS_USER_WIDTH-1:0] dma_m_axis_write_desc_status_user;
logic [3:0] dma_m_axis_write_desc_status_error;
logic dma_m_axis_write_desc_status_valid;
logic [AXIS_DATA_WIDTH-1:0] dma_m_axis_read_data_tdata;
logic [AXIS_KEEP_WIDTH-1:0] dma_m_axis_read_data_tkeep;
logic dma_m_axis_read_data_tvalid;
@ -190,18 +196,18 @@ module axi_dma_if_wrapper #(
.clk (clk),
.rst (rst),
.s_axis_read_desc_addr (s_axis_read_desc_addr),
.s_axis_read_desc_len (s_axis_read_desc_len),
.s_axis_read_desc_tag (s_axis_read_desc_tag),
.s_axis_read_desc_id (s_axis_read_desc_id),
.s_axis_read_desc_dest (s_axis_read_desc_dest),
.s_axis_read_desc_user (s_axis_read_desc_user),
.s_axis_read_desc_valid (s_axis_read_desc_valid),
.s_axis_read_desc_ready (s_axis_read_desc_ready),
.s_axis_read_desc_addr (dma_s_axis_read_desc_addr),
.s_axis_read_desc_len (dma_s_axis_read_desc_len),
.s_axis_read_desc_tag (dma_s_axis_read_desc_tag),
.s_axis_read_desc_id (dma_s_axis_read_desc_id),
.s_axis_read_desc_dest (dma_s_axis_read_desc_dest),
.s_axis_read_desc_user (dma_s_axis_read_desc_user),
.s_axis_read_desc_valid (dma_s_axis_read_desc_valid),
.s_axis_read_desc_ready (dma_s_axis_read_desc_ready),
.m_axis_read_desc_status_tag (m_axis_read_desc_status_tag),
.m_axis_read_desc_status_error (m_axis_read_desc_status_error),
.m_axis_read_desc_status_valid (m_axis_read_desc_status_valid),
.m_axis_read_desc_status_tag (dma_m_axis_read_desc_status_tag),
.m_axis_read_desc_status_error (dma_m_axis_read_desc_status_error),
.m_axis_read_desc_status_valid (dma_m_axis_read_desc_status_valid),
.m_axis_read_data_tdata (dma_m_axis_read_data_tdata),
.m_axis_read_data_tkeep (dma_m_axis_read_data_tkeep),
@ -212,19 +218,19 @@ module axi_dma_if_wrapper #(
.m_axis_read_data_tdest (dma_m_axis_read_data_tdest),
.m_axis_read_data_tuser (dma_m_axis_read_data_tuser),
.s_axis_write_desc_addr (s_axis_write_desc_addr),
.s_axis_write_desc_len (s_axis_write_desc_len),
.s_axis_write_desc_tag (s_axis_write_desc_tag),
.s_axis_write_desc_valid (s_axis_write_desc_valid),
.s_axis_write_desc_ready (s_axis_write_desc_ready),
.s_axis_write_desc_addr (dma_s_axis_write_desc_addr),
.s_axis_write_desc_len (dma_s_axis_write_desc_len),
.s_axis_write_desc_tag (dma_s_axis_write_desc_tag),
.s_axis_write_desc_valid (dma_s_axis_write_desc_valid),
.s_axis_write_desc_ready (dma_s_axis_write_desc_ready),
.m_axis_write_desc_status_len (m_axis_write_desc_status_len),
.m_axis_write_desc_status_tag (m_axis_write_desc_status_tag),
.m_axis_write_desc_status_id (m_axis_write_desc_status_id),
.m_axis_write_desc_status_dest (m_axis_write_desc_status_dest),
.m_axis_write_desc_status_user (m_axis_write_desc_status_user),
.m_axis_write_desc_status_error (m_axis_write_desc_status_error),
.m_axis_write_desc_status_valid (m_axis_write_desc_status_valid),
.m_axis_write_desc_status_len (dma_m_axis_write_desc_status_len),
.m_axis_write_desc_status_tag (dma_m_axis_write_desc_status_tag),
.m_axis_write_desc_status_id (dma_m_axis_write_desc_status_id),
.m_axis_write_desc_status_dest (dma_m_axis_write_desc_status_dest),
.m_axis_write_desc_status_user (dma_m_axis_write_desc_status_user),
.m_axis_write_desc_status_error (dma_m_axis_write_desc_status_error),
.m_axis_write_desc_status_valid (dma_m_axis_write_desc_status_valid),
.s_axis_write_data_tdata (dma_s_axis_write_data_tdata),
.s_axis_write_data_tkeep (dma_s_axis_write_data_tkeep),
@ -280,6 +286,68 @@ module axi_dma_if_wrapper #(
.write_abort (write_abort)
);
// local read descriptor interface -> DMA flat input
axi_dma_read_desc_if_to_flat #(
.ADDR_W (AXI_ADDR_WIDTH),
.LEN_W (LEN_WIDTH),
.TAG_W (TAG_WIDTH),
.ID_W (AXIS_ID_WIDTH),
.DEST_W (AXIS_DEST_WIDTH),
.USER_W (AXIS_USER_WIDTH)
) u_s_axis_read_desc_if_to_flat (
.s_axis_read_desc (s_axis_read_desc),
.m_axis_read_desc_addr (dma_s_axis_read_desc_addr),
.m_axis_read_desc_len (dma_s_axis_read_desc_len),
.m_axis_read_desc_tag (dma_s_axis_read_desc_tag),
.m_axis_read_desc_id (dma_s_axis_read_desc_id),
.m_axis_read_desc_dest (dma_s_axis_read_desc_dest),
.m_axis_read_desc_user (dma_s_axis_read_desc_user),
.m_axis_read_desc_valid (dma_s_axis_read_desc_valid),
.m_axis_read_desc_ready (dma_s_axis_read_desc_ready)
);
// DMA read descriptor status flat output -> local status interface
axi_dma_read_desc_status_flat_to_if #(
.TAG_W (TAG_WIDTH)
) u_m_axis_read_desc_status_flat_to_if (
.m_axis_read_desc_status_tag (dma_m_axis_read_desc_status_tag),
.m_axis_read_desc_status_error (dma_m_axis_read_desc_status_error),
.m_axis_read_desc_status_valid (dma_m_axis_read_desc_status_valid),
.m_axis_read_desc_status (m_axis_read_desc_status)
);
// local write descriptor interface -> DMA flat input
axi_dma_write_desc_if_to_flat #(
.ADDR_W (AXI_ADDR_WIDTH),
.LEN_W (LEN_WIDTH),
.TAG_W (TAG_WIDTH)
) u_s_axis_write_desc_if_to_flat (
.s_axis_write_desc (s_axis_write_desc),
.m_axis_write_desc_addr (dma_s_axis_write_desc_addr),
.m_axis_write_desc_len (dma_s_axis_write_desc_len),
.m_axis_write_desc_tag (dma_s_axis_write_desc_tag),
.m_axis_write_desc_valid (dma_s_axis_write_desc_valid),
.m_axis_write_desc_ready (dma_s_axis_write_desc_ready)
);
// DMA write descriptor status flat output -> local status interface
axi_dma_write_desc_status_flat_to_if #(
.LEN_W (LEN_WIDTH),
.TAG_W (TAG_WIDTH),
.ID_W (AXIS_ID_WIDTH),
.DEST_W (AXIS_DEST_WIDTH),
.USER_W (AXIS_USER_WIDTH)
) u_m_axis_write_desc_status_flat_to_if (
.m_axis_write_desc_status_len (dma_m_axis_write_desc_status_len),
.m_axis_write_desc_status_tag (dma_m_axis_write_desc_status_tag),
.m_axis_write_desc_status_id (dma_m_axis_write_desc_status_id),
.m_axis_write_desc_status_dest (dma_m_axis_write_desc_status_dest),
.m_axis_write_desc_status_user (dma_m_axis_write_desc_status_user),
.m_axis_write_desc_status_error (dma_m_axis_write_desc_status_error),
.m_axis_write_desc_status_valid (dma_m_axis_write_desc_status_valid),
.m_axis_write_desc_status (m_axis_write_desc_status)
);
// DMA read data flat output -> local axis_if.master
axis_flat_to_if #(
.DATA_W (AXIS_DATA_WIDTH),