baulin.fa/reflectometer_fpga_project
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efcd6ef5d0fd72a8baf97b9465976689a432f813
reflectometer_fpga_project/designs/adc_dac_synchoronizer/debug.xdc
Zer0Nu11 efcd6ef5d0 upd: 
fast fix of sampler OTR.
fix debug.xdc
Major add of full automated testing for TB.
2026-06-20 03:07:05 +03:00

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Tcl
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# Primary clocks
create_clock -name geneartor_clk -period 8.000 [get_ports clk_dac]
create_clock -name sampler_clk -period 15.385 [get_ports clk_adc]
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