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baulin.fa
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reflectometer_fpga_project
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e4677003681c180d1b59075c0e53cc3eaa9f7011
reflectometer_fpga_project
/
rtl
/
controller
/
tests
History
Phil
e467700368
tests: update testbench for controller reg map
2026-07-14 16:34:35 +03:00
..
controller_tb.sv
add window_size register
2026-07-10 14:15:17 +03:00
Makefile
infra: add build Makefile for controller test project
2026-04-15 13:31:28 +03:00
tb_control_behav.wcfg
add window_size register
2026-07-10 14:15:17 +03:00
tb_controller_wrapper_axil.sv
tests: update testbench for controller reg map
2026-07-14 16:34:35 +03:00
test_controller.py
tests: update testbench for controller reg map
2026-07-14 16:34:35 +03:00
test_timing.xdc
tests: add controller tb
2026-04-15 13:30:56 +03:00
