129 lines
3.4 KiB
Systemverilog
129 lines
3.4 KiB
Systemverilog
module tb_controller_wrapper_axil #(
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parameter int unsigned DAC_DATA_WIDTH = 12,
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parameter int unsigned ADDR_W = 16,
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parameter int unsigned DATA_W = 32,
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parameter int unsigned USER_W = 1
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)(
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input logic ctrl_clk,
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input logic rst,
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input logic [ADDR_W-1:0] s_axil_awaddr,
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input logic [2:0] s_axil_awprot,
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input logic s_axil_awvalid,
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output logic s_axil_awready,
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input logic [DATA_W-1:0] s_axil_wdata,
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input logic [DATA_W/8-1:0] s_axil_wstrb,
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input logic s_axil_wvalid,
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output logic s_axil_wready,
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output logic [1:0] s_axil_bresp,
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output logic s_axil_bvalid,
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input logic s_axil_bready,
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input logic [ADDR_W-1:0] s_axil_araddr,
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input logic [2:0] s_axil_arprot,
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input logic s_axil_arvalid,
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output logic s_axil_arready,
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output logic [DATA_W-1:0] s_axil_rdata,
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output logic [1:0] s_axil_rresp,
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output logic s_axil_rvalid,
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input logic s_axil_rready
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);
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logic rst_n;
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assign rst_n = ~rst;
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logic dac_clk_in;
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logic adc_clk_in;
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assign dac_clk_in = ctrl_clk;
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assign adc_clk_in = ctrl_clk;
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logic finish;
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assign finish = 1'b0;
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axi4l_if #(
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.ADDR_W(ADDR_W),
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.DATA_W(DATA_W),
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.USER_W(USER_W)
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) axil_bus (
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.aclk(ctrl_clk),
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.aresetn(rst_n)
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);
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axi4l_flat_to_if #(
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.ADDR_W(ADDR_W),
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.DATA_W(DATA_W),
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.USER_W(USER_W)
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) u_flat_to_if (
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.s_axil_awaddr (s_axil_awaddr),
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.s_axil_awprot (s_axil_awprot),
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.s_axil_awvalid(s_axil_awvalid),
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.s_axil_awready(s_axil_awready),
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.s_axil_wdata (s_axil_wdata),
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.s_axil_wstrb (s_axil_wstrb),
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.s_axil_wvalid (s_axil_wvalid),
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.s_axil_wready (s_axil_wready),
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.s_axil_bresp (s_axil_bresp),
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.s_axil_bvalid (s_axil_bvalid),
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.s_axil_bready (s_axil_bready),
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.s_axil_araddr (s_axil_araddr),
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.s_axil_arprot (s_axil_arprot),
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.s_axil_arvalid(s_axil_arvalid),
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.s_axil_arready(s_axil_arready),
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.s_axil_rdata (s_axil_rdata),
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.s_axil_rresp (s_axil_rresp),
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.s_axil_rvalid (s_axil_rvalid),
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.s_axil_rready (s_axil_rready),
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.m_axil(axil_bus)
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);
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logic [31:0] adc_window_size;
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logic [31:0] dac_pulse_width;
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logic [31:0] dac_pulse_period;
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logic [DAC_DATA_WIDTH-1:0] dac_pulse_height;
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logic [15:0] dac_pulse_num;
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logic [31:0] adc_pulse_period;
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logic [15:0] adc_pulse_num;
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logic dac_start;
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logic adc_start;
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logic dac_rst;
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logic adc_rst;
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controller_wrapper_axil #(
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.DAC_DATA_WIDTH(DAC_DATA_WIDTH),
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.ADDR_W(ADDR_W),
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.DATA_W(DATA_W),
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.USER_W(USER_W)
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) dut (
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.ctrl_clk(ctrl_clk),
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.dac_clk_in(dac_clk_in),
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.adc_clk_in(adc_clk_in),
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.rst_n(rst_n),
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.s_axil(axil_bus),
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.finish(finish),
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.adc_window_size(adc_window_size),
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.dac_pulse_width(dac_pulse_width),
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.dac_pulse_period(dac_pulse_period),
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.dac_pulse_height(dac_pulse_height),
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.dac_pulse_num(dac_pulse_num),
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.adc_pulse_period(adc_pulse_period),
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.adc_pulse_num(adc_pulse_num),
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.dac_start(dac_start),
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.adc_start(adc_start),
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.dac_rst(dac_rst),
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.adc_rst(adc_rst)
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);
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endmodule
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