249 lines
6.3 KiB
Systemverilog
249 lines
6.3 KiB
Systemverilog
`timescale 1ns / 1ps
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module tb_mac_test;
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reg rst_n = 1'b0;
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reg gmii_rx_clk = 1'b0;
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reg gmii_tx_clk = 1'b0;
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reg gmii_rx_dv = 1'b0;
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reg [7:0] gmii_rxd = 8'h00;
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wire gmii_tx_en;
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wire [7:0] gmii_txd;
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wire [7:0] m_axis_rx_tdata;
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wire m_axis_rx_tvalid;
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reg m_axis_rx_tready = 1'b0;
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wire m_axis_rx_tlast;
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int cnt = 0;
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// ============================================================
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// DUT
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// ============================================================
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axis_mac dut (
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.rst_n(rst_n),
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.gmii_tx_clk(gmii_tx_clk),
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.gmii_rx_clk(gmii_rx_clk),
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.gmii_rx_dv(gmii_rx_dv),
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.gmii_rxd(gmii_rxd),
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.gmii_tx_en(gmii_tx_en),
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.gmii_txd(gmii_txd),
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.m_axis_rx_tdata(m_axis_rx_tdata),
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.m_axis_rx_tvalid(m_axis_rx_tvalid),
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.m_axis_rx_tready(m_axis_rx_tready),
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.m_axis_rx_tlast(m_axis_rx_tlast)
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);
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// ============================================================
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// Clocks
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// ============================================================
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always #4 gmii_rx_clk = ~gmii_rx_clk;
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always #4 gmii_tx_clk = ~gmii_tx_clk;
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// ============================================================
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// Helpers
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// ============================================================
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task automatic gmii_idle;
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input integer cycles;
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integer i;
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begin
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gmii_rx_dv <= 1'b0;
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gmii_rxd <= 8'h00;
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for (i = 0; i < cycles; i = i + 1) begin
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@(posedge gmii_rx_clk);
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end
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end
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endtask
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task automatic send_gmii_byte;
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input [7:0] b;
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begin
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@(posedge gmii_rx_clk);
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gmii_rx_dv <= 1'b1;
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gmii_rxd <= b;
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end
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endtask
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task automatic end_gmii_frame;
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begin
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@(posedge gmii_rx_clk);
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gmii_rx_dv <= 1'b0;
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gmii_rxd <= 8'h00;
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end
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endtask
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task automatic send_gmii_frame;
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input integer frame_len;
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input [8*2048-1:0] frame_data_flat;
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integer i;
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reg [7:0] current_byte;
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begin
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gmii_idle(12);
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for (i = 0; i < frame_len; i = i + 1) begin
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current_byte = frame_data_flat[i*8 +: 8];
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send_gmii_byte(current_byte);
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end
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end_gmii_frame();
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// inter-frame gap
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gmii_idle(12);
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end
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endtask
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reg [7:0] frame_mem [0:2047];
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task automatic send_gmii_frame_mem;
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input integer frame_len;
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integer i;
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begin
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gmii_idle(12);
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for (i = 0; i < frame_len; i = i + 1) begin
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send_gmii_byte(frame_mem[i]);
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end
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end_gmii_frame();
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gmii_idle(12);
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end
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endtask
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// ============================================================
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// Monitor AXIS RX
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// ============================================================
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always @(posedge gmii_rx_clk) begin
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if (m_axis_rx_tvalid && m_axis_rx_tready) begin
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$write("%02x ", m_axis_rx_tdata);
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if (m_axis_rx_tlast)
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$write("<TLAST>");
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end
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cnt = cnt + 1;
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if (cnt % 8 < 6) begin
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m_axis_rx_tready = 1'b1;
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end else m_axis_rx_tready = 1'b0;
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end
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// ============================================================
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// Test sequence
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// ============================================================
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integer i;
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initial begin
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// init
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gmii_rx_dv = 1'b0;
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gmii_rxd = 8'h00;
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rst_n = 1'b0;
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gmii_idle(200);
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rst_n = 1'b1;
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gmii_idle(200);
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frame_mem[0] = 8'h55;
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frame_mem[1] = 8'h55;
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frame_mem[2] = 8'h55;
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frame_mem[3] = 8'h55;
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frame_mem[4] = 8'h55;
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frame_mem[5] = 8'h55;
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frame_mem[6] = 8'h55;
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frame_mem[7] = 8'hd5;
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frame_mem[8] = 8'h00;
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frame_mem[9] = 8'h0a;
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frame_mem[10] = 8'h35;
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frame_mem[11] = 8'h01;
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frame_mem[12] = 8'hfe;
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frame_mem[13] = 8'hc0;
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frame_mem[14] = 8'h30;
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frame_mem[15] = 8'h56;
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frame_mem[16] = 8'h0f;
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frame_mem[17] = 8'ha0;
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frame_mem[18] = 8'h12;
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frame_mem[19] = 8'hec;
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frame_mem[20] = 8'h08;
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frame_mem[21] = 8'h00;
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frame_mem[22] = 8'h45;
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frame_mem[23] = 8'h00;
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frame_mem[24] = 8'h00;
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frame_mem[25] = 8'h23;
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frame_mem[26] = 8'h65;
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frame_mem[27] = 8'hfa;
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frame_mem[28] = 8'h40;
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frame_mem[29] = 8'h00;
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frame_mem[30] = 8'h40;
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frame_mem[31] = 8'h11;
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frame_mem[32] = 8'h53;
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frame_mem[33] = 8'h7a;
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frame_mem[34] = 8'hc0;
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frame_mem[35] = 8'ha8;
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frame_mem[36] = 8'h00;
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frame_mem[37] = 8'h03;
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frame_mem[38] = 8'hc0;
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frame_mem[39] = 8'ha8;
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frame_mem[40] = 8'h00;
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frame_mem[41] = 8'h02;
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frame_mem[42] = 8'hc0;
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frame_mem[43] = 8'h31;
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frame_mem[44] = 8'h1f;
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frame_mem[45] = 8'h90;
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frame_mem[46] = 8'h00;
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frame_mem[47] = 8'h0f;
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frame_mem[48] = 8'he4;
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frame_mem[49] = 8'h7f;
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frame_mem[50] = 8'h6e;
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frame_mem[51] = 8'h65;
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frame_mem[52] = 8'h77;
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frame_mem[53] = 8'h5f;
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frame_mem[54] = 8'h6d;
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frame_mem[55] = 8'h73;
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frame_mem[56] = 8'h67;
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// FCS
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frame_mem[57] = 8'h00;
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frame_mem[58] = 8'h00;
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frame_mem[59] = 8'h00;
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frame_mem[60] = 8'h00;
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frame_mem[61] = 8'h00;
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frame_mem[62] = 8'h00;
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frame_mem[63] = 8'h00;
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frame_mem[64] = 8'h00;
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frame_mem[65] = 8'h00;
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frame_mem[66] = 8'h00;
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frame_mem[67] = 8'h00;
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frame_mem[68] = 8'h8c;
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frame_mem[69] = 8'ha2;
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frame_mem[70] = 8'h2e;
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frame_mem[71] = 8'h26;
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frame_mem[72] = 8'hdd;
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send_gmii_frame_mem(73);
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gmii_idle(200);
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send_gmii_frame_mem(57);
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gmii_idle(20);
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send_gmii_frame_mem(57);
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gmii_idle(200);
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send_gmii_frame_mem(66);
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gmii_idle(200);
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send_gmii_frame_mem(66);
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send_gmii_frame_mem(66);
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gmii_idle(200);
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$display("\nSimulation done");
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$finish;
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end
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endmodule |