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reflectometer_fpga_project/designs/adc_dac_synchoronizer/debug.xdc
2026-05-06 14:41:15 +03:00

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Tcl

# Primary clocks
create_clock -name eth_clk -period 8.000 [get_ports dac_clk_in]
create_clock -name acc_clk -period 15.385 [get_ports adc_clk_in]
# Asynchronous clock groups
set_clock_groups -name ASYNC_ETH_ACC -asynchronous \
-group [get_clocks eth_clk] \
-group [get_clocks acc_clk]