reflectometer_fpga_project/rtl/controller/tests/tb_controller_wrapper_axil.sv

module tb_controller_wrapper_axil #(
  parameter int unsigned ADDR_W             = 16,
  parameter int unsigned DATA_W             = 32,
  parameter int unsigned USER_W             = 1,

  parameter int unsigned DAC_DATA_WIDTH     = 12,

  parameter int unsigned AXI_ADDR_WIDTH     = 16,
  parameter int unsigned AXIS_ID_WIDTH      = 8,
  parameter int unsigned LEN_WIDTH          = 20,
  parameter int unsigned AXIS_USER_WIDTH    = 1,
  parameter int unsigned AXIS_DEST_WIDTH    = 8,
  parameter int unsigned TAG_WIDTH          = 8,

  parameter int unsigned READ_DESC_WIDTH    = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH,
  parameter int unsigned WRITE_DESC_WIDTH   = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH,

  parameter int unsigned READ_STATUS_WIDTH  = TAG_WIDTH + 4,
  parameter int unsigned WRITE_STATUS_WIDTH = LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH + 4
)(
  input  logic                 ctrl_clk,
  input  logic                 rst,

  input  logic [ADDR_W-1:0]   s_axil_awaddr,
  input  logic [2:0]          s_axil_awprot,
  input  logic                s_axil_awvalid,
  output logic                s_axil_awready,

  input  logic [DATA_W-1:0]   s_axil_wdata,
  input  logic [DATA_W/8-1:0] s_axil_wstrb,
  input  logic                s_axil_wvalid,
  output logic                s_axil_wready,

  output logic [1:0]          s_axil_bresp,
  output logic                s_axil_bvalid,
  input  logic                s_axil_bready,

  input  logic [ADDR_W-1:0]   s_axil_araddr,
  input  logic [2:0]          s_axil_arprot,
  input  logic                s_axil_arvalid,
  output logic                s_axil_arready,

  output logic [DATA_W-1:0]   s_axil_rdata,
  output logic [1:0]          s_axil_rresp,
  output logic                s_axil_rvalid,
  input  logic                s_axil_rready
);

  logic rst_n;
  assign rst_n = ~rst;

  // Для минимального теста держим все clock domain-ы на одном clock.
  logic dac_clk_in;
  logic adc_clk_in;
  assign dac_clk_in = ctrl_clk;
  assign adc_clk_in = ctrl_clk;

  logic finish;
  assign finish = 1'b0;

  axi4l_if #(
    .ADDR_W(ADDR_W),
    .DATA_W(DATA_W),
    .USER_W(USER_W)
  ) axil_bus (
    .aclk(ctrl_clk),
    .aresetn(rst_n)
  );

  axi4l_flat_to_if #(
    .ADDR_W(ADDR_W),
    .DATA_W(DATA_W),
    .USER_W(USER_W)
  ) u_flat_to_if (
    .s_axil_awaddr (s_axil_awaddr),
    .s_axil_awprot (s_axil_awprot),
    .s_axil_awvalid(s_axil_awvalid),
    .s_axil_awready(s_axil_awready),

    .s_axil_wdata  (s_axil_wdata),
    .s_axil_wstrb  (s_axil_wstrb),
    .s_axil_wvalid (s_axil_wvalid),
    .s_axil_wready (s_axil_wready),

    .s_axil_bresp  (s_axil_bresp),
    .s_axil_bvalid (s_axil_bvalid),
    .s_axil_bready (s_axil_bready),

    .s_axil_araddr (s_axil_araddr),
    .s_axil_arprot (s_axil_arprot),
    .s_axil_arvalid(s_axil_arvalid),
    .s_axil_arready(s_axil_arready),

    .s_axil_rdata  (s_axil_rdata),
    .s_axil_rresp  (s_axil_rresp),
    .s_axil_rvalid (s_axil_rvalid),
    .s_axil_rready (s_axil_rready),

    .m_axil(axil_bus)
  );

  // Controller ADC/DAC outputs.
  logic [31:0]               adc_window_size;
  logic [31:0]               dac_pulse_width;
  logic [31:0]               dac_pulse_period;
  logic [DAC_DATA_WIDTH-1:0] dac_pulse_height;
  logic [15:0]               dac_pulse_num;
  logic [31:0]               adc_pulse_period;
  logic [15:0]               adc_pulse_num;
  logic                      dac_start;
  logic                      adc_start;
  logic                      dac_rst;
  logic                      adc_rst;

  // DMA side. Для базового AXI-Lite теста даём спокойные значения.
  logic ready_desc_read;
  logic ready_desc_write;
  logic ready_status_read;
  logic ready_status_write;

  logic valid_desc_read;
  logic valid_desc_write;
  logic valid_status_read;
  logic valid_status_write;

  logic [READ_STATUS_WIDTH-1:0]  status_read_cmd_in;
  logic [WRITE_STATUS_WIDTH-1:0] status_write_cmd_in;

  logic [READ_DESC_WIDTH-1:0]    desc_read_cmd_out;
  logic [WRITE_DESC_WIDTH-1:0]   desc_write_cmd_out;

  assign ready_desc_read      = 1'b1;
  assign ready_desc_write     = 1'b1;
  assign valid_status_read    = 1'b0;
  assign valid_status_write   = 1'b0;
  assign status_read_cmd_in   = '0;
  assign status_write_cmd_in  = '0;

  controller_wrapper_axil #(
    .ADDR_W(ADDR_W),
    .DATA_W(DATA_W),
    .USER_W(USER_W),
    .DAC_DATA_WIDTH(DAC_DATA_WIDTH),
    .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
    .AXIS_ID_WIDTH(AXIS_ID_WIDTH),
    .LEN_WIDTH(LEN_WIDTH),
    .AXIS_USER_WIDTH(AXIS_USER_WIDTH),
    .AXIS_DEST_WIDTH(AXIS_DEST_WIDTH),
    .TAG_WIDTH(TAG_WIDTH),
    .READ_DESC_WIDTH(READ_DESC_WIDTH),
    .WRITE_DESC_WIDTH(WRITE_DESC_WIDTH),
    .READ_STATUS_WIDTH(READ_STATUS_WIDTH),
    .WRITE_STATUS_WIDTH(WRITE_STATUS_WIDTH)
  ) dut (
    .ctrl_clk(ctrl_clk),
    .dac_clk_in(dac_clk_in),
    .adc_clk_in(adc_clk_in),
    .rst_n(rst_n),
    .s_axil(axil_bus),

    .finish(finish),
    .adc_window_size(adc_window_size),

    .dac_pulse_width(dac_pulse_width),
    .dac_pulse_period(dac_pulse_period),
    .dac_pulse_height(dac_pulse_height),
    .dac_pulse_num(dac_pulse_num),

    .adc_pulse_period(adc_pulse_period),
    .adc_pulse_num(adc_pulse_num),

    .dac_start(dac_start),
    .adc_start(adc_start),
    .dac_rst(dac_rst),
    .adc_rst(adc_rst),

    .ready_desc_read(ready_desc_read),
    .ready_desc_write(ready_desc_write),

    .ready_status_read(ready_status_read),
    .ready_status_write(ready_status_write),

    .valid_desc_read(valid_desc_read),
    .valid_desc_write(valid_desc_write),

    .valid_status_read(valid_status_read),
    .valid_status_write(valid_status_write),

    .status_read_cmd_in(status_read_cmd_in),
    .status_write_cmd_in(status_write_cmd_in),

    .desc_read_cmd_out(desc_read_cmd_out),
    .desc_write_cmd_out(desc_write_cmd_out)
  );

endmodule