21 lines
336 B
Verilog
21 lines
336 B
Verilog
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module reset(
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input clk,
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input key1,
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output rst_n
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);
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reg[27:0] cnt = 28'd0;
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reg rst_n_reg;
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assign rst_n = rst_n_reg;
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always@(posedge clk)
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if(key1==1'b0)
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cnt <= 0;
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else
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if(cnt != 28'h3ffffff)
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cnt <= cnt + 1'd1;
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else
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cnt <= cnt;
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always@(posedge clk)
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rst_n_reg <= (cnt == 28'h3ffffff);
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endmodule
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