435 lines
15 KiB
Systemverilog
435 lines
15 KiB
Systemverilog
// ethernet MAC with axi stream IO with UDP
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`timescale 1 ns / 1 ns
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module axis_mac
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(
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input rst_n,
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input gmii_tx_clk,
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input gmii_rx_clk,
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input gmii_rx_dv,
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input [7:0] gmii_rxd,
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output reg gmii_tx_en,
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output reg [7:0] gmii_txd,
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// AXI-stream RX output (clock domain = gmii_rx_clk)
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(* MARK_DEBUG="true" *)output reg [7:0] m_axis_rx_tdata,
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(* MARK_DEBUG="true" *)output reg m_axis_rx_tvalid,
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(* MARK_DEBUG="true" *)input wire m_axis_rx_tready,
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(* MARK_DEBUG="true" *)output reg m_axis_rx_tlast,
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(* MARK_DEBUG="true" *)output wire [15:0] udp_rec_data_length,
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// tx part
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(* MARK_DEBUG="true" *)input wire send_req,
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input wire [15:0] data_length,
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(* MARK_DEBUG="true" *)output reg req_ready,
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(* MARK_DEBUG="true" *)input wire [7:0] s_axis_tx_tdata,
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(* MARK_DEBUG="true" *)input wire s_axis_tx_tvalid,
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(* MARK_DEBUG="true" *)output reg s_axis_tx_tready,
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(* MARK_DEBUG="true" *)input wire s_axis_tx_tlast
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);
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// ----------------------------------------------------------------
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// GMII RX input registering
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// ----------------------------------------------------------------
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reg gmii_rx_dv_d0;
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reg [7:0] gmii_rxd_d0;
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always @(posedge gmii_rx_clk or negedge rst_n) begin
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if (!rst_n) begin
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gmii_rx_dv_d0 <= 1'b0;
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gmii_rxd_d0 <= 8'd0;
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end else begin
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gmii_rx_dv_d0 <= gmii_rx_dv;
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gmii_rxd_d0 <= gmii_rxd;
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end
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end
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// ----------------------------------------------------------------
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// TX path from mac_top
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// ----------------------------------------------------------------
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wire gmii_tx_en_tmp;
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wire [7:0] gmii_txd_tmp;
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always @(posedge gmii_tx_clk or negedge rst_n) begin
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if (!rst_n) begin
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gmii_tx_en <= 1'b0;
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gmii_txd <= 8'd0;
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end else begin
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gmii_tx_en <= gmii_tx_en_tmp;
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gmii_txd <= gmii_txd_tmp;
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end
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end
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// TX signals
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reg [7:0] tx_ram_wr_data;
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reg tx_ram_wr_en;
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reg [15:0] udp_send_data_length;
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reg udp_tx_req;
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reg arp_request_req;
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wire mac_send_end;
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wire udp_ram_data_req;
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wire udp_tx_end;
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wire almost_full;
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(* MARK_DEBUG="true" *)wire arp_found;
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wire mac_not_exist;
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wire [15:0] udp_ram_data_count;
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// RX signals
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reg [10:0] udp_rec_ram_read_addr;
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wire [7:0] udp_rec_ram_rdata;
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wire udp_rec_data_valid;
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mac_top mac_top0 (
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.gmii_tx_clk (gmii_tx_clk),
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.gmii_rx_clk (gmii_rx_clk),
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.rst_n (rst_n),
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.source_mac_addr (48'h00_0a_35_01_fe_c0),
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.TTL (8'h80),
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.source_ip_addr (32'hc0a80002), // 192.168.0.2
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.destination_ip_addr (32'hc0a80003), // 192.168.0.3
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.udp_send_source_port (16'h1f90), // 8080
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.udp_send_destination_port (16'h1f90), // 8080
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.ram_wr_data (tx_ram_wr_data),
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.ram_wr_en (tx_ram_wr_en),
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.udp_ram_data_req (udp_ram_data_req),
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.udp_send_data_length (udp_send_data_length),
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.udp_tx_end (udp_tx_end),
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.almost_full (almost_full),
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.udp_tx_req (udp_tx_req),
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.arp_request_req (arp_request_req),
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.mac_send_end (mac_send_end),
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.mac_data_valid (gmii_tx_en_tmp),
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.mac_tx_data (gmii_txd_tmp),
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.rx_dv (gmii_rx_dv_d0),
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.mac_rx_datain (gmii_rxd_d0),
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.udp_rec_ram_rdata (udp_rec_ram_rdata),
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.udp_rec_ram_read_addr (udp_rec_ram_read_addr),
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.udp_rec_data_length (udp_rec_data_length),
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.udp_rec_data_valid (udp_rec_data_valid),
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.arp_found (arp_found),
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.mac_not_exist (mac_not_exist)
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);
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// Detect "new packet ready" on udp_rec_data_valid rising edge
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reg udp_rec_data_valid_d0;
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always @(posedge gmii_rx_clk or negedge rst_n) begin
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if (!rst_n)
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udp_rec_data_valid_d0 <= 1'b0;
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else
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udp_rec_data_valid_d0 <= udp_rec_data_valid;
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end
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wire udp_pkt_done = udp_rec_data_valid & ~udp_rec_data_valid_d0;
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// ----------------------------------------------------------------
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// RX RAM -> AXI-stream bridge
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//
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// Assumption:
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// udp_rec_data_length includes 8-byte UDP header,
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// so payload length = udp_rec_data_length - 8
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//
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// This implementation is simple and safe:
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// - start on udp_pkt_done
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// - read bytes 0 .. payload_len-1 from RX RAM
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// - output them on AXIS
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//
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// ----------------------------------------------------------------
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localparam RX_IDLE = 2'd0;
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localparam RX_NOTREADY = 2'd1;
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localparam RX_START = 2'd2;
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localparam RX_DATA = 2'd3;
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(* MARK_DEBUG="true" *) reg [1:0] rx_state;
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(* MARK_DEBUG="true" *) reg [15:0] rx_payload_len;
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(* MARK_DEBUG="true" *) reg [15:0] rx_index;
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always @(posedge gmii_rx_clk or negedge rst_n) begin
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if (!rst_n) begin
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rx_state <= RX_IDLE;
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rx_payload_len <= 16'd0;
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rx_index <= 16'd0;
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udp_rec_ram_read_addr <= 11'd0;
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m_axis_rx_tdata <= 8'd0;
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m_axis_rx_tvalid <= 1'b0;
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m_axis_rx_tlast <= 1'b0;
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end else begin
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case (rx_state)
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RX_IDLE: begin
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m_axis_rx_tvalid <= 1'b0;
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m_axis_rx_tlast <= 1'b0;
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rx_index <= 16'd0;
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udp_rec_ram_read_addr <= 11'd0;
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if (udp_pkt_done) begin
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// protect against pathological short values
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if (udp_rec_data_length > 16'd8) begin
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rx_payload_len <= udp_rec_data_length - 16'd8;
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udp_rec_ram_read_addr <= 11'd0; // issue read for byte 0
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rx_state <= RX_NOTREADY;
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end else begin
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rx_payload_len <= 16'd0;
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rx_state <= RX_IDLE;
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end
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end
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end
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// one cycle for synchronous BRAM read latency
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RX_NOTREADY: begin
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m_axis_rx_tvalid <= 1'b0;
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m_axis_rx_tlast <= 1'b0;
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if (m_axis_rx_tready)
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rx_state <= RX_START;
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end
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RX_START: begin
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if (m_axis_rx_tready) begin
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// put current data
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// end of data?
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if (rx_index == (rx_payload_len - 1)) begin
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rx_state <= RX_IDLE;
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end else begin
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rx_state <= RX_DATA;
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end
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// always increment pointer
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rx_index <= rx_index + 1'b1;
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udp_rec_ram_read_addr <= rx_index + 1'b1; // next byte
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end else begin
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rx_state <= RX_NOTREADY;
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end
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end
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RX_DATA: begin
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// hold valid until accepted
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if (!m_axis_rx_tready) begin
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// take a break while not ready
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m_axis_rx_tvalid <= m_axis_rx_tvalid;
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m_axis_rx_tlast <= m_axis_rx_tlast;
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rx_state <= RX_NOTREADY;
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// reset increment
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rx_index <= rx_index - 1'b1;
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udp_rec_ram_read_addr <= rx_index - 1'b1;
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end else begin
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// present current byte from RAM
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m_axis_rx_tdata <= udp_rec_ram_rdata;
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m_axis_rx_tvalid <= 1'b1;
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m_axis_rx_tlast <= (rx_index == (rx_payload_len));
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if (rx_index == (rx_payload_len)) begin
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// last byte accepted immediately if ready=1,
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// otherwise valid/last remain asserted until ready
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rx_state <= RX_IDLE;
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end
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rx_index <= rx_index + 1'b1;
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udp_rec_ram_read_addr <= rx_index + 1'b1; // next byte
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end
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end
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default: begin
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rx_state <= RX_IDLE;
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m_axis_rx_tvalid <= 1'b0;
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m_axis_rx_tlast <= 1'b0;
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end
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endcase
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end
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end
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// ----------------------------------------------------------------
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// TX FSM
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// Semantics:
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// - send_req/data_length form a packet send request
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// - udp_tx_req is held HIGH until udp_ram_data_req pulses
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// - udp_ram_data_req is a pulse - start feeding payload now to RAM
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// - AXIS ready is asserted only during payload write phase
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// ----------------------------------------------------------------
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localparam TX_IDLE = 3'd0;
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localparam TX_ARP_REQ = 3'd1;
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localparam TX_ARP_SEND = 3'd2;
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localparam TX_WAIT_ARP = 3'd3;
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localparam TX_WAIT_RAM_REQ = 3'd4;
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localparam TX_STREAM = 3'd5;
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localparam TX_WAIT_DRAIN = 3'd6;
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(* MARK_DEBUG="true" *)reg [2:0] tx_state;
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assign arp_request_req = (tx_state == TX_ARP_REQ) ;
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reg [15:0] tx_req_len;
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reg [15:0] tx_bytes_written;
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reg [15:0] tx_release_threshold;
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reg tx_req_inflight;
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// register for long arp timeout, if no got no response
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reg [31:0] arp_delay;
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reg arp_cached;
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always @(posedge gmii_tx_clk or negedge rst_n) begin
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if (!rst_n) begin
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tx_state <= TX_IDLE;
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tx_ram_wr_data <= 8'd0;
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arp_cached <= 1'b0;
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tx_ram_wr_en <= 1'b0;
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udp_send_data_length <= 16'd0;
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udp_tx_req <= 1'b0;
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arp_delay <= 32'b0;
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s_axis_tx_tready <= 1'b0;
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req_ready <= 1'b0;
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tx_req_len <= 16'd0;
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tx_bytes_written <= 16'd0;
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tx_release_threshold <= 16'd0;
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tx_req_inflight <= 1'b0;
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end else begin
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// defaults
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tx_ram_wr_en <= 1'b0;
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case (tx_state)
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// Ready to accept a new packet request
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TX_IDLE: begin
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udp_tx_req <= 1'b0;
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s_axis_tx_tready <= 1'b0;
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tx_bytes_written <= 16'd0;
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tx_req_inflight <= 1'b0;
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req_ready <= arp_cached && !almost_full;
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if (send_req && req_ready) begin
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tx_req_len <= data_length;
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udp_send_data_length <= data_length;
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tx_req_inflight <= 1'b1;
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// threshold for allowing next packet
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// to be written to the RAM
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if (data_length > 16'd16)
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tx_release_threshold <= data_length - 16'd16;
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else
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tx_release_threshold <= 16'd0;
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tx_state <= TX_WAIT_RAM_REQ;
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end
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// arp check
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if (!arp_cached) begin
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tx_state <= TX_ARP_REQ;
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end
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end
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// Pulse ARP request
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TX_ARP_REQ: begin
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req_ready <= 1'b0;
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s_axis_tx_tready <= 1'b0;
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udp_tx_req <= 1'b0;
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arp_delay <= 32'ha000000;
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tx_state <= TX_ARP_SEND;
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end
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// Wait until ARP is resolved
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TX_ARP_SEND: begin
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req_ready <= 1'b0;
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s_axis_tx_tready <= 1'b0;
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udp_tx_req <= 1'b0;
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// sent
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if (mac_send_end)
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tx_state <= TX_WAIT_ARP;
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end
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// wait for ARP response
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TX_WAIT_ARP: begin
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if (arp_found) begin
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arp_cached <= 1'b1;
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tx_state <= TX_IDLE;
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end
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// timeout to not spam ARPs
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if (arp_delay == 32'b0) begin
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// re-try
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tx_state <= TX_ARP_REQ;
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end else begin
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// wait
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arp_delay = arp_delay - 32'b1;
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end
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end
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// Hold udp_tx_req until udp_ram_data_req pulse arrives
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TX_WAIT_RAM_REQ: begin
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req_ready <= 1'b0;
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udp_tx_req <= 1'b1;
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if (udp_ram_data_req) begin
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udp_tx_req <= 1'b0;
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s_axis_tx_tready <= 1'b1;
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tx_state <= TX_STREAM;
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end
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end
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// Accept AXIS bytes and write them into TX RAM
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TX_STREAM: begin
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req_ready <= 1'b0;
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udp_tx_req <= 1'b0;
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// keep ready high while receiving payload bytes
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s_axis_tx_tready <= (tx_bytes_written < tx_req_len);
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if (s_axis_tx_tvalid && s_axis_tx_tready) begin
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tx_ram_wr_data <= s_axis_tx_tdata;
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tx_ram_wr_en <= 1'b1;
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tx_bytes_written <= tx_bytes_written + 1'b1;
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if (tx_bytes_written + 1'b1 >= tx_req_len) begin
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s_axis_tx_tready <= 1'b0;
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tx_state <= TX_WAIT_DRAIN;
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end
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end
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end
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// Packet payload is already in RAM.
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// Wait until TX RAM starts draining enough to allow
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// the next request.
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TX_WAIT_DRAIN: begin
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s_axis_tx_tready <= 1'b0;
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udp_tx_req <= 1'b0;
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if (udp_ram_data_count <= tx_release_threshold)
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tx_state <= TX_IDLE;
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end
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default: begin
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tx_state <= TX_IDLE;
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tx_ram_wr_en <= 1'b0;
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udp_tx_req <= 1'b0;
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s_axis_tx_tready <= 1'b0;
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req_ready <= 1'b0;
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end
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endcase
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end
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end
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endmodule |