76 lines
2.5 KiB
Makefile
76 lines
2.5 KiB
Makefile
TOPLEVEL_LANG = verilog
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SIM ?= verilator
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PWD := $(shell pwd)
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WRAP_DIR = $(PWD)/../src
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RTL_CTRL_DIR = $(PWD)/../../controller_new/src
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RTL_ACCUM_DIR = $(PWD)/../../accum/src
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RTL_GENERATOR_DIR = $(PWD)/../../generator/src
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RTL_SAMPLER_DIR = $(PWD)/../../sampler/src
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RTL_ADC_DAC_MODELS_DIR = $(PWD)/../reflectometer_base
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LIBS_DIR = $(PWD)/../../../external/rtl_libs
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#axi primitives
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VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_pkg.sv
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VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_if.sv
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VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axis_if.sv
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VERILOG_SOURCES += $(LIBS_DIR)/axi/axi_reg/axi4l_reg_map.sv
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#dma primitives
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VERILOG_SOURCES += $(RTL_CTRL_DIR)/dma_reg_pkg.sv
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VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_rd.v
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VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma_wr.v
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VERILOG_SOURCES += $(LIBS_DIR)/external/verilog-axi/rtl/axi_dma.v
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VERILOG_SOURCES += $(WRAP_DIR)/axi_dma_wrapper_if.sv
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# controller primitives
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VERILOG_SOURCES += $(RTL_CTRL_DIR)/controller.sv
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VERILOG_SOURCES += $(RTL_CTRL_DIR)/dma_controller.sv
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VERILOG_SOURCES += $(RTL_CTRL_DIR)/shaper_axis_desc.sv
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VERILOG_SOURCES += $(RTL_CTRL_DIR)/shaper_axis_status.sv
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VERILOG_SOURCES += $(RTL_CTRL_DIR)/controller_wrapper_axil.sv
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VERILOG_SOURCES += $(RTL_CTRL_DIR)/axi4l_reg_map_controller_pkg.sv
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VERILOG_SOURCES += $(RTL_CTRL_DIR)/axis_defaults_helper.sv
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VERILOG_SOURCES += $(RTL_CTRL_DIR)/axi4l_reg_map_controller.sv
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# accumulator primitives
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VERILOG_SOURCES += $(RTL_ACCUM_DIR)/adder.sv
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VERILOG_SOURCES += $(RTL_ACCUM_DIR)/accum.sv
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VERILOG_SOURCES += $(RTL_ACCUM_DIR)/out_axis_fifo.sv
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VERILOG_SOURCES += $(RTL_ACCUM_DIR)/accum_top.sv
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# generator primitives
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VERILOG_SOURCES += $(RTL_GENERATOR_DIR)/generator.sv
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#sampler_primitives
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VERILOG_SOURCES += $(RTL_SAMPLER_DIR)/sampler.sv
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# project primitives
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VERILOG_SOURCES += $(WRAP_DIR)/reflectometer_ip.sv
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VERILOG_SOURCES += $(WRAP_DIR)/reflectometer_and_dma_wrapper.sv
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# testbench primitives
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VERILOG_SOURCES += $(RTL_ADC_DAC_MODELS_DIR)/adc_model.sv
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VERILOG_SOURCES += $(RTL_ADC_DAC_MODELS_DIR)/dac_model.sv
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VERILOG_SOURCES += $(PWD)/tb_reflectometer_and_dma_wrapper.sv
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TOPLEVEL = tb_reflectometer_and_dma_wrapper
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MODULE = test_reflectometer_and_dma
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ifeq ($(SIM),verilator)
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EXTRA_ARGS += --trace --trace-structs
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EXTRA_ARGS += -I$(LIBS_DIR)/axi/rtl/
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COMPILE_ARGS += -Wno-fatal
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COMPILE_ARGS += -I$(LIBS_DIR)/axi/rtl/
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EXTRA_ARGS += --trace
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EXTRA_ARGS += --trace-structs
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EXTRA_ARGS += --public-flat-rw
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EXTRA_ARGS += -Wno-fatal
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EXTRA_ARGS += --timing
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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