42 lines
1.1 KiB
Systemverilog
42 lines
1.1 KiB
Systemverilog
package dma_reg_pkg;
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parameter int unsigned AXI_ADDR_WIDTH = 16;
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parameter int unsigned LEN_WIDTH = 20;
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parameter int unsigned TAG_WIDTH = 8;
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parameter int unsigned AXIS_ID_WIDTH = 8;
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parameter int unsigned AXIS_DEST_WIDTH = 8;
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parameter int unsigned AXIS_USER_WIDTH = 1;
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typedef struct packed {
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logic [AXIS_USER_WIDTH-1:0] user;
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logic [AXIS_DEST_WIDTH-1:0] dest;
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logic [AXIS_ID_WIDTH-1:0] id;
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logic [TAG_WIDTH-1:0] tag;
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logic [LEN_WIDTH-1:0] len;
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logic [AXI_ADDR_WIDTH-1:0] addr;
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} dma_read_desc_t;
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typedef struct packed {
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logic [TAG_WIDTH-1:0] tag;
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logic [LEN_WIDTH-1:0] len;
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logic [AXI_ADDR_WIDTH-1:0] addr;
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} dma_write_desc_t;
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typedef struct packed {
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logic [3:0] error;
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logic [TAG_WIDTH-1:0] tag;
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} dma_read_status_t;
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typedef struct packed {
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logic [3:0] error;
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logic [AXIS_USER_WIDTH-1:0] user;
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logic [AXIS_DEST_WIDTH-1:0] dest;
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logic [AXIS_ID_WIDTH-1:0] id;
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logic [TAG_WIDTH-1:0] tag;
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logic [LEN_WIDTH-1:0] len;
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} dma_write_status_t;
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endpackage |