339 lines
11 KiB
Systemverilog
339 lines
11 KiB
Systemverilog
module tb_controller_wrapper_axil #(
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parameter int unsigned ADDR_W = 16,
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parameter int unsigned DATA_W = 32,
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parameter int unsigned USER_W = 1,
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parameter int unsigned DAC_DATA_WIDTH = 12,
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parameter int unsigned AXI_ADDR_WIDTH = 16,
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parameter int unsigned AXIS_ID_WIDTH = 8,
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parameter int unsigned LEN_WIDTH = 20,
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parameter int unsigned AXIS_USER_WIDTH = 1,
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parameter int unsigned AXIS_DEST_WIDTH = 8,
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parameter int unsigned TAG_WIDTH = 8,
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parameter int unsigned READ_DESC_WIDTH = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH,
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parameter int unsigned WRITE_DESC_WIDTH = AXI_ADDR_WIDTH + LEN_WIDTH + TAG_WIDTH,
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parameter int unsigned READ_STATUS_WIDTH = TAG_WIDTH + 4,
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parameter int unsigned WRITE_STATUS_WIDTH = LEN_WIDTH + TAG_WIDTH + AXIS_ID_WIDTH + AXIS_DEST_WIDTH + AXIS_USER_WIDTH + 4,
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// ceil(width / 8), чтобы keep/strb не стали слишком узкими для нестандартных ширин типа 12/49/61.
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parameter int unsigned READ_DESC_KEEP_W = (READ_DESC_WIDTH + 7) / 8,
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parameter int unsigned WRITE_DESC_KEEP_W = (WRITE_DESC_WIDTH + 7) / 8,
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parameter int unsigned READ_STATUS_KEEP_W = (READ_STATUS_WIDTH + 7) / 8,
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parameter int unsigned WRITE_STATUS_KEEP_W = (WRITE_STATUS_WIDTH + 7) / 8
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)(
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input logic ctrl_clk,
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input logic rst,
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input logic [ADDR_W-1:0] s_axil_awaddr,
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input logic [2:0] s_axil_awprot,
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input logic s_axil_awvalid,
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output logic s_axil_awready,
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input logic [DATA_W-1:0] s_axil_wdata,
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input logic [DATA_W/8-1:0] s_axil_wstrb,
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input logic s_axil_wvalid,
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output logic s_axil_wready,
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output logic [1:0] s_axil_bresp,
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output logic s_axil_bvalid,
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input logic s_axil_bready,
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input logic [ADDR_W-1:0] s_axil_araddr,
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input logic [2:0] s_axil_arprot,
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input logic s_axil_arvalid,
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output logic s_axil_arready,
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output logic [DATA_W-1:0] s_axil_rdata,
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output logic [1:0] s_axil_rresp,
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output logic s_axil_rvalid,
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input logic s_axil_rready,
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// ---------------------------------------------------------------------------
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// Минимальный flat-view для DMA AXIS портов.
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// Наружу оставлены только tdata/tvalid/tready в старом стиле.
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// Все остальные AXIS поля внутри обёртки завязаны на безопасные значения.
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// ---------------------------------------------------------------------------
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// DUT master -> testbench: descriptor commands.
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output logic [READ_DESC_WIDTH-1:0] desc_read_cmd_out,
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output logic valid_desc_read,
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input logic ready_desc_read,
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output logic [WRITE_DESC_WIDTH-1:0] desc_write_cmd_out,
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output logic valid_desc_write,
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input logic ready_desc_write,
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// testbench -> DUT slave: status commands.
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input logic [READ_STATUS_WIDTH-1:0] status_read_cmd_in,
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input logic valid_status_read,
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output logic ready_status_read,
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input logic [WRITE_STATUS_WIDTH-1:0] status_write_cmd_in,
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input logic valid_status_write,
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output logic ready_status_write
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);
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logic rst_n;
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assign rst_n = ~rst;
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// Для минимального теста держим все clock domain-ы на одном clock.
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logic dac_clk_in;
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logic adc_clk_in;
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assign dac_clk_in = ctrl_clk;
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assign adc_clk_in = ctrl_clk;
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logic finish;
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assign finish = 1'b0;
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// ---------------------------------------------------------------------------
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// AXI-Lite flat -> axi4l_if
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// ---------------------------------------------------------------------------
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axi4l_if #(
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.ADDR_W(ADDR_W),
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.DATA_W(DATA_W),
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.USER_W(USER_W)
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) axil_bus (
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.aclk(ctrl_clk),
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.aresetn(rst_n)
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);
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axi4l_flat_to_if #(
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.ADDR_W(ADDR_W),
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.DATA_W(DATA_W),
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.USER_W(USER_W)
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) u_axil_flat_to_if (
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.s_axil_awaddr (s_axil_awaddr),
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.s_axil_awprot (s_axil_awprot),
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.s_axil_awvalid(s_axil_awvalid),
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.s_axil_awready(s_axil_awready),
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.s_axil_wdata (s_axil_wdata),
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.s_axil_wstrb (s_axil_wstrb),
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.s_axil_wvalid (s_axil_wvalid),
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.s_axil_wready (s_axil_wready),
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.s_axil_bresp (s_axil_bresp),
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.s_axil_bvalid (s_axil_bvalid),
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.s_axil_bready (s_axil_bready),
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.s_axil_araddr (s_axil_araddr),
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.s_axil_arprot (s_axil_arprot),
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.s_axil_arvalid(s_axil_arvalid),
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.s_axil_arready(s_axil_arready),
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.s_axil_rdata (s_axil_rdata),
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.s_axil_rresp (s_axil_rresp),
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.s_axil_rvalid (s_axil_rvalid),
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.s_axil_rready (s_axil_rready),
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.m_axil(axil_bus)
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);
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// ---------------------------------------------------------------------------
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// AXIS interfaces for the updated controller_wrapper_axil
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// ---------------------------------------------------------------------------
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axis_if #(
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.DATA_W(READ_STATUS_WIDTH),
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.KEEP_W(READ_STATUS_KEEP_W),
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.ID_W(AXIS_ID_WIDTH),
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.DEST_W(AXIS_DEST_WIDTH),
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.USER_W(AXIS_USER_WIDTH)
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) axis_status_read (
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.aclk(ctrl_clk),
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.aresetn(rst_n)
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);
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axis_if #(
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.DATA_W(WRITE_STATUS_WIDTH),
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.KEEP_W(WRITE_STATUS_KEEP_W),
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.ID_W(AXIS_ID_WIDTH),
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.DEST_W(AXIS_DEST_WIDTH),
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.USER_W(AXIS_USER_WIDTH)
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) axis_status_write (
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.aclk(ctrl_clk),
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.aresetn(rst_n)
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);
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axis_if #(
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.DATA_W(READ_DESC_WIDTH),
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.KEEP_W(READ_DESC_KEEP_W),
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.ID_W(AXIS_ID_WIDTH),
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.DEST_W(AXIS_DEST_WIDTH),
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.USER_W(AXIS_USER_WIDTH)
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) axis_desc_read (
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.aclk(ctrl_clk),
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.aresetn(rst_n)
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);
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axis_if #(
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.DATA_W(WRITE_DESC_WIDTH),
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.KEEP_W(WRITE_DESC_KEEP_W),
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.ID_W(AXIS_ID_WIDTH),
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.DEST_W(AXIS_DEST_WIDTH),
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.USER_W(AXIS_USER_WIDTH)
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) axis_desc_write (
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.aclk(ctrl_clk),
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.aresetn(rst_n)
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);
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// testbench flat status -> DUT AXIS slave ports
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axis_flat_to_if #(
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.DATA_W(READ_STATUS_WIDTH),
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.KEEP_W(READ_STATUS_KEEP_W),
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.ID_W(AXIS_ID_WIDTH),
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.DEST_W(AXIS_DEST_WIDTH),
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.USER_W(AXIS_USER_WIDTH)
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) u_status_read_flat_to_if (
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.s_axis_tdata (status_read_cmd_in),
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.s_axis_tkeep ({READ_STATUS_KEEP_W{1'b1}}),
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.s_axis_tstrb ({READ_STATUS_KEEP_W{1'b1}}),
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.s_axis_tlast (1'b1),
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.s_axis_tid ('0),
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.s_axis_tdest ('0),
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.s_axis_tuser ('0),
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.s_axis_tvalid(valid_status_read),
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.s_axis_tready(ready_status_read),
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.m_axis(axis_status_read)
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);
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axis_flat_to_if #(
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.DATA_W(WRITE_STATUS_WIDTH),
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.KEEP_W(WRITE_STATUS_KEEP_W),
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.ID_W(AXIS_ID_WIDTH),
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.DEST_W(AXIS_DEST_WIDTH),
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.USER_W(AXIS_USER_WIDTH)
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) u_status_write_flat_to_if (
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.s_axis_tdata (status_write_cmd_in),
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.s_axis_tkeep ({WRITE_STATUS_KEEP_W{1'b1}}),
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.s_axis_tstrb ({WRITE_STATUS_KEEP_W{1'b1}}),
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.s_axis_tlast (1'b1),
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.s_axis_tid ('0),
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.s_axis_tdest ('0),
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.s_axis_tuser ('0),
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.s_axis_tvalid(valid_status_write),
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.s_axis_tready(ready_status_write),
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.m_axis(axis_status_write)
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);
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// DUT AXIS master ports -> testbench flat descriptor outputs
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logic [READ_DESC_KEEP_W-1:0] unused_desc_read_tkeep;
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logic [READ_DESC_KEEP_W-1:0] unused_desc_read_tstrb;
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logic unused_desc_read_tlast;
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logic [AXIS_ID_WIDTH-1:0] unused_desc_read_tid;
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logic [AXIS_DEST_WIDTH-1:0] unused_desc_read_tdest;
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logic [AXIS_USER_WIDTH-1:0] unused_desc_read_tuser;
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axis_if_to_flat #(
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.DATA_W(READ_DESC_WIDTH),
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.KEEP_W(READ_DESC_KEEP_W),
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.ID_W(AXIS_ID_WIDTH),
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.DEST_W(AXIS_DEST_WIDTH),
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.USER_W(AXIS_USER_WIDTH)
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) u_desc_read_if_to_flat (
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.s_axis(axis_desc_read),
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.m_axis_tdata (desc_read_cmd_out),
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.m_axis_tkeep (unused_desc_read_tkeep),
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.m_axis_tstrb (unused_desc_read_tstrb),
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.m_axis_tlast (unused_desc_read_tlast),
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.m_axis_tid (unused_desc_read_tid),
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.m_axis_tdest (unused_desc_read_tdest),
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.m_axis_tuser (unused_desc_read_tuser),
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.m_axis_tvalid(valid_desc_read),
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.m_axis_tready(ready_desc_read)
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);
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logic [WRITE_DESC_KEEP_W-1:0] unused_desc_write_tkeep;
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logic [WRITE_DESC_KEEP_W-1:0] unused_desc_write_tstrb;
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logic unused_desc_write_tlast;
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logic [AXIS_ID_WIDTH-1:0] unused_desc_write_tid;
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logic [AXIS_DEST_WIDTH-1:0] unused_desc_write_tdest;
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logic [AXIS_USER_WIDTH-1:0] unused_desc_write_tuser;
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axis_if_to_flat #(
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.DATA_W(WRITE_DESC_WIDTH),
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.KEEP_W(WRITE_DESC_KEEP_W),
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.ID_W(AXIS_ID_WIDTH),
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.DEST_W(AXIS_DEST_WIDTH),
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.USER_W(AXIS_USER_WIDTH)
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) u_desc_write_if_to_flat (
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.s_axis(axis_desc_write),
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.m_axis_tdata (desc_write_cmd_out),
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.m_axis_tkeep (unused_desc_write_tkeep),
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.m_axis_tstrb (unused_desc_write_tstrb),
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.m_axis_tlast (unused_desc_write_tlast),
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.m_axis_tid (unused_desc_write_tid),
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.m_axis_tdest (unused_desc_write_tdest),
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.m_axis_tuser (unused_desc_write_tuser),
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.m_axis_tvalid(valid_desc_write),
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.m_axis_tready(ready_desc_write)
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);
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// Controller ADC/DAC outputs.
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logic [31:0] adc_window_size;
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logic [31:0] dac_pulse_width;
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logic [31:0] dac_pulse_period;
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logic [DAC_DATA_WIDTH-1:0] dac_pulse_height;
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logic [15:0] dac_pulse_num;
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logic [31:0] adc_pulse_period;
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logic [15:0] adc_pulse_num;
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logic dac_start;
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logic adc_start;
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logic dac_rst;
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logic adc_rst;
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controller_wrapper_axil #(
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.ADDR_W(ADDR_W),
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.DATA_W(DATA_W),
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.USER_W(USER_W),
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.DAC_DATA_WIDTH(DAC_DATA_WIDTH),
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.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
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.AXIS_ID_WIDTH(AXIS_ID_WIDTH),
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.LEN_WIDTH(LEN_WIDTH),
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.AXIS_USER_WIDTH(AXIS_USER_WIDTH),
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.AXIS_DEST_WIDTH(AXIS_DEST_WIDTH),
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.TAG_WIDTH(TAG_WIDTH),
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.READ_DESC_WIDTH(READ_DESC_WIDTH),
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.WRITE_DESC_WIDTH(WRITE_DESC_WIDTH),
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.READ_STATUS_WIDTH(READ_STATUS_WIDTH),
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.WRITE_STATUS_WIDTH(WRITE_STATUS_WIDTH)
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) dut (
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.ctrl_clk(ctrl_clk),
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.dac_clk_in(dac_clk_in),
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.adc_clk_in(adc_clk_in),
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.rst_n(rst_n),
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.s_axil(axil_bus),
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.finish(finish),
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.adc_window_size(adc_window_size),
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.dac_pulse_width(dac_pulse_width),
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.dac_pulse_period(dac_pulse_period),
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.dac_pulse_height(dac_pulse_height),
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.dac_pulse_num(dac_pulse_num),
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.adc_pulse_period(adc_pulse_period),
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.adc_pulse_num(adc_pulse_num),
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.dac_start(dac_start),
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.adc_start(adc_start),
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.dac_rst(dac_rst),
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.adc_rst(adc_rst),
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.s_axis_status_read(axis_status_read),
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.s_axis_status_write(axis_status_write),
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.m_axis_desc_read(axis_desc_read),
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.m_axis_desc_write(axis_desc_write)
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);
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endmodule : tb_controller_wrapper_axil
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