178 lines
4.8 KiB
Verilog
178 lines
4.8 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Module Name: ethernet_test
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//////////////////////////////////////////////////////////////////////////////////
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module gmii_arbi
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(
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input clk,
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input rst_n,
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input [1:0] speed,
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input link,
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(* MARK_DEBUG="true" *)input gmii_rx_dv,
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(* MARK_DEBUG="true" *)input [7:0] gmii_rxd,
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(* MARK_DEBUG="true" *)input gmii_tx_en,
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(* MARK_DEBUG="true" *)input [7:0] gmii_txd,
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output reg [31:0] pack_total_len, //delay time
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output e_rst_n,
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(* MARK_DEBUG="true" *)output reg e_rx_dv,
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(* MARK_DEBUG="true" *)output reg [7:0] e_rxd,
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(* MARK_DEBUG="true" *)output reg e_tx_en,
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(* MARK_DEBUG="true" *)output reg [7:0] e_txd
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);
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reg eth_1000m_en ;
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wire eth_10_100m_en ;
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reg eth_100m_en ;
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reg eth_10m_en ;
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reg [1:0] speed_d0 ;
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reg [1:0] speed_d1 ;
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reg [1:0] speed_d2 ;
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reg link_d0 ;
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reg link_d1 ;
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reg link_d2 ;
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wire e10_100_tx_en ;
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wire [7:0] e10_100_txd ;
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wire e10_100_rx_dv ;
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wire [7:0] e10_100_rxd ;
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reg e_rst_en ;
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reg [7:0] e_rst_cnt ;
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assign e_rst_n = link_d2 & e_rst_en ;
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always @(posedge clk or negedge rst_n)
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begin
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if (~rst_n)
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begin
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speed_d0 <= 2'b00 ;
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speed_d1 <= 2'b00 ;
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speed_d2 <= 2'b00 ;
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link_d0 <= 1'b0 ;
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link_d1 <= 1'b0 ;
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link_d2 <= 1'b0 ;
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end
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else
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begin
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speed_d0 <= speed ;
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speed_d1 <= speed_d0 ;
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speed_d2 <= speed_d1 ;
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link_d0 <= link ;
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link_d1 <= link_d0 ;
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link_d2 <= link_d1 ;
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end
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end
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always @(posedge clk or negedge rst_n)
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begin
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if (~rst_n)
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begin
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eth_1000m_en <= 1'b0 ;
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eth_100m_en <= 1'b0 ;
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eth_10m_en <= 1'b0 ;
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pack_total_len <= 32'd2500000 ;
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end
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else if (speed_d2 == 2'b10) //1000M
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begin
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eth_1000m_en <= 1'b1 ;
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eth_100m_en <= 1'b0 ;
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eth_10m_en <= 1'b0 ;
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pack_total_len <= 32'd125000000 ; //1s
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end
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else if (speed_d2 == 2'b01) //100M
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begin
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eth_1000m_en <= 1'b0 ;
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eth_100m_en <= 1'b1 ;
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eth_10m_en <= 1'b0 ;
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pack_total_len <= 32'd25000000 ; //1s
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end
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else if (speed_d2 == 2'b00) //10M
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begin
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eth_1000m_en <= 1'b0 ;
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eth_100m_en <= 1'b0 ;
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eth_10m_en <= 1'b1 ;
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pack_total_len <= 32'd2500000 ; //1s
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end
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end
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always @(posedge clk or negedge rst_n)
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begin
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if (~rst_n)
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begin
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e_rx_dv <= 1'b0 ;
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e_rxd <= 8'd0 ;
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e_tx_en <= 1'b0 ;
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e_txd <= 8'd0 ;
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end
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else if (eth_1000m_en)
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begin
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e_rx_dv <= gmii_rx_dv ;
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e_rxd <= gmii_rxd ;
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e_tx_en <= gmii_tx_en ;
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e_txd <= gmii_txd ;
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end
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else if (eth_100m_en | eth_10m_en)
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begin
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e_rx_dv <= e10_100_rx_dv ;
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e_rxd <= e10_100_rxd ;
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e_tx_en <= e10_100_tx_en ;
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e_txd <= e10_100_txd ;
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end
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end
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always @(posedge clk or negedge rst_n)
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begin
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if (~rst_n)
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e_rst_en <= 1'b1 ;
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else if (speed_d2 != speed_d1)
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e_rst_en <= 1'b0 ;
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else if (e_rst_cnt == 8'd200)
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e_rst_en <= 1'b1 ;
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end
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always @(posedge clk or negedge rst_n)
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begin
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if (~rst_n)
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e_rst_cnt <= 8'd0 ;
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else if (~e_rst_en)
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e_rst_cnt <= e_rst_cnt + 1'b1 ;
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else
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e_rst_cnt <= 8'd0 ;
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end
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assign eth_10_100m_en = eth_100m_en | eth_10m_en ;
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gmii_tx_buffer tx_buffer_inst
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(
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.clk (clk ),
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.rst_n (e_rst_n ),
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.eth_10_100m_en (eth_10_100m_en ),
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.link (e_rst_n ),
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.gmii_tx_en (gmii_tx_en ),
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.gmii_txd (gmii_txd ),
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.e10_100_tx_en (e10_100_tx_en ),
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.e10_100_txd (e10_100_txd )
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);
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gmii_rx_buffer rx_buffer_inst
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(
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.clk (clk ),
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.rst_n (e_rst_n ),
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.link (e_rst_n ),
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.eth_100m_en (eth_100m_en ),
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.eth_10m_en (eth_10m_en ),
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.gmii_rx_dv (gmii_rx_dv ),
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.gmii_rxd (gmii_rxd ),
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.e10_100_rx_dv (e10_100_rx_dv ),
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.e10_100_rxd (e10_100_rxd )
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);
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endmodule
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