105 lines
2.1 KiB
Systemverilog
105 lines
2.1 KiB
Systemverilog
`timescale 1ns / 1ps
|
|
|
|
module generator_tb;
|
|
|
|
parameter DATA_WIDTH = 14;
|
|
parameter CLK_PERIOD = 16;
|
|
|
|
logic clk;
|
|
logic rst;
|
|
logic start;
|
|
|
|
logic [31:0] pulse_width;
|
|
logic [31:0] pulse_period;
|
|
logic [DATA_WIDTH-1:0] pulse_height;
|
|
logic [15:0] pulse_num;
|
|
|
|
logic pulse;
|
|
logic [DATA_WIDTH-1:0] pulse_height_out;
|
|
|
|
// DUT
|
|
generator #(
|
|
.DATA_WIDTH(DATA_WIDTH)
|
|
) dut (
|
|
.clk_in(clk),
|
|
.rst(rst),
|
|
.start(start),
|
|
.pulse_width(pulse_width),
|
|
.pulse_period(pulse_period),
|
|
.pulse_height(pulse_height),
|
|
.pulse_num(pulse_num),
|
|
.pulse(pulse),
|
|
.pulse_height_out(pulse_height_out)
|
|
);
|
|
|
|
// Clock
|
|
initial begin
|
|
clk = 0;
|
|
forever #(CLK_PERIOD/2) clk = ~clk;
|
|
end
|
|
|
|
initial begin
|
|
$display("\n=== GENERATOR TEST ===\n");
|
|
|
|
rst = 1;
|
|
start = 0;
|
|
|
|
pulse_width = 0;
|
|
pulse_period = 0;
|
|
pulse_height = 0;
|
|
pulse_num = 0;
|
|
|
|
repeat(5) @(posedge clk);
|
|
rst = 0;
|
|
|
|
// --- Test 1 ---
|
|
// 3 clk 1, 5 clk 0, 4 pulses
|
|
repeat(2) @(posedge clk);
|
|
pulse_width = 3;
|
|
pulse_period = 8;
|
|
pulse_num = 4;
|
|
pulse_height = 14'h3FF;
|
|
start = 1;
|
|
|
|
repeat(1) @(posedge clk);
|
|
start = 0;
|
|
|
|
repeat(50) @(posedge clk);
|
|
|
|
// --- Test 2 ---
|
|
$display("\n--- SECOND RUN ---\n");
|
|
|
|
@(posedge clk);
|
|
pulse_width = 2;
|
|
pulse_period = 5;
|
|
pulse_num = 3;
|
|
pulse_height = 14'h155;
|
|
start = 1;
|
|
|
|
@(posedge clk);
|
|
start = 0;
|
|
|
|
repeat(40) @(posedge clk);
|
|
|
|
pulse_width = 3;
|
|
pulse_period = 8;
|
|
pulse_num = 4;
|
|
pulse_height = 14'h3FF;
|
|
start = 1;
|
|
|
|
repeat(1) @(posedge clk);
|
|
start = 0;
|
|
|
|
repeat(50) @(posedge clk);
|
|
|
|
$display("\n=== TEST FINISHED ===");
|
|
$finish;
|
|
end
|
|
|
|
// Display
|
|
always @(posedge clk) begin
|
|
$display("t=%0t | pulse=%0b | height=%h",
|
|
$time, pulse, pulse_height_out);
|
|
end
|
|
|
|
endmodule |