Files
reflectometer_fpga_project/designs/reflectometer_base/debug.xdc

9 lines
460 B
Tcl

# Primary clocks
create_clock -name ref_clock -period 5.000 [get_ports clk_in]
create_clock -name phy_rx_clock -period 8.000 [get_ports clk_m_axis]
create_clock -name phy_tx_clock -period 8.000 [get_ports clk_s_axis]
set clk_125_name [get_clocks -of_objects [get_pins generator_inst/clk_dac_125]]
set clk_65_name [get_clocks -of_objects [get_pins accumulator_top_dut/clk_adc_65]]
set_clock_groups -asynchronous -group $clk_125_name -group $clk_65_name