41 lines
1.3 KiB
Makefile
41 lines
1.3 KiB
Makefile
TOPLEVEL_LANG = verilog
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SIM ?= verilator
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PWD := $(shell pwd)
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RTL_DIR = $(PWD)/../src
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LIBS_DIR = $(PWD)/../../../external/rtl_libs
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VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_pkg.sv
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VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi_if.sv
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VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi4l_flat_to_if.sv
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VERILOG_SOURCES += $(LIBS_DIR)/axi/rtl/axi4l_if_to_flat.sv
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VERILOG_SOURCES += $(LIBS_DIR)/axi/axi_reg/axi4l_reg_map.sv
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VERILOG_SOURCES += $(RTL_DIR)/controller.sv
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VERILOG_SOURCES += $(RTL_DIR)/dma_controller.sv
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VERILOG_SOURCES += $(RTL_DIR)/shaper_axis_desc.sv
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VERILOG_SOURCES += $(RTL_DIR)/shaper_axis_status.sv
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VERILOG_SOURCES += $(RTL_DIR)/controller_wrapper_axil.sv
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VERILOG_SOURCES += $(RTL_DIR)/axi4l_reg_map_controller_pkg.sv
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VERILOG_SOURCES += $(RTL_DIR)/axi4l_reg_map_controller.sv
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VERILOG_SOURCES += $(PWD)/tb_controller_wrapper_axil.sv
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TOPLEVEL = tb_controller_wrapper_axil
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MODULE = test_controller
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ifeq ($(SIM),verilator)
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EXTRA_ARGS += --trace --trace-structs
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EXTRA_ARGS += -I$(LIBS_DIR)/axi/rtl/
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COMPILE_ARGS += -Wno-fatal
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COMPILE_ARGS += -I$(LIBS_DIR)/axi/rtl/
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EXTRA_ARGS += --trace
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EXTRA_ARGS += --trace-structs
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EXTRA_ARGS += --public-flat-rw
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EXTRA_ARGS += -Wno-fatal
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EXTRA_ARGS += --timing
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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