babintsev.lv
7c7cd451b8
add: reference signal generation, correlation metrics functions, baseline test task fix: small fixes of ports and code refactoring
681 lines
23 KiB
Systemverilog
681 lines
23 KiB
Systemverilog
`timescale 1ns / 1ps
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`include "interfaces.svh"
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// start push
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`define DEBUG
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`define MEASURE_CLK(clk, period) \
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begin \
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realtime t1, t2; \
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@(posedge clk); \
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t1 = $realtime; \
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@(posedge clk); \
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t2 = $realtime; \
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period = t2 - t1; \
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end
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module reflectometer_tb;
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//------------------------------------------------------------
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// Параметры
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//------------------------------------------------------------
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localparam int unsigned DAC_DATA_WIDTH = 14;
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localparam int unsigned ADC_DATA_WIDTH = 12;
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localparam LOGIC_ZERO_LEVEL = 0; // DAC -5V for logic zero
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localparam VOLTAGE_ZERO_LEVEL = 2**(DAC_DATA_WIDTH-1); // DAC 0V for logic zero
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localparam PACK_FACTOR = 1; // not used in TB
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localparam PROCESS_MODE = 0; // 0 - uint, 1 - int. Current accumulator don't support signed sum
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localparam ACCUM_WIDTH = 32; // accumulator number bit witdth
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localparam N_MAX = 4096; // max value of windows to average by experiments
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localparam PACKET_SIZE = 1024; // bytes per UDP packet
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localparam int REQUEST_TIMEOUT = 3 * PACKET_SIZE; // timeout for packet receiving from accumulator
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localparam ZERO_LEVEL = LOGIC_ZERO_LEVEL; // "logic" VS "voltage"
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localparam CLK_ETH_PHY_PERIOD = 8.000; // 125 MHz
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localparam CLK_REF_PERIOD = 5.000; // 200 MHz
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//------------------------------------------------------------
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// Глобальные перменные
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//------------------------------------------------------------
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realtime CLK_ADC_PERIOD;
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realtime CLK_DAC_PERIOD;
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//------------------------------------------------------------
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// Тактовые сигналы и сброс
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//------------------------------------------------------------
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logic clk_ref = 1'b0; // 200 MHz
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logic clk_eth_phy = 1'b0; // common for RX & TX
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logic rst_n = 1'b0;
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//------------------------------------------------------------
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// Управление и конфиг DUT
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//------------------------------------------------------------
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logic [31:0] window_size_port;
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// AXI-S интерфейс для управления
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axis_if axis_control_if (
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.clk(clk_eth_phy),
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.rst_n(rst_n)
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);
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//------------------------------------------------------------
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// Входы DUT
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//------------------------------------------------------------
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// ADC интерфейс
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wire clk_adc;
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wire adc_otr;
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wire [ADC_DATA_WIDTH-1:0] adc_data;
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//------------------------------------------------------------
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// Выходы
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//------------------------------------------------------------
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// Статусы
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wire mmcm_locked;
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wire workflow_done;
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wire processing_done;
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// DAC интерфейс
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wire clk_dac;
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wire dac_wrt;
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wire [DAC_DATA_WIDTH-1:0] dac_data;
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// AXI-S интерфейс для данных
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axis_if axis_accumulator_if (
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.clk(clk_eth_phy),
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.rst_n(rst_n)
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);
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//------------------------------------------------------------
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// Внутренние сигналы тестбенча
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//------------------------------------------------------------
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// Интерфейс хендшейка с MAC-PHY
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wire send_request;
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logic request_ready;
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// Сигнал между ЦАП и АЦП
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real signal_voltage;
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//------------------------------------------------------------
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// Virtual DAC
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//------------------------------------------------------------
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virtual_dac_model #( // default voltage range is +/- 5V
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.DAC_DATA_WIDTH(DAC_DATA_WIDTH)
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// ,.VOLTAGE_GAIN(2)
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) virtual_dac (
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.clk_i(clk_dac),
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.wrt_i(dac_wrt),
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.data_i(dac_data),
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.voltage_o(signal_voltage)
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);
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//------------------------------------------------------------
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// Virtual ADC
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//------------------------------------------------------------
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virtual_adc_model #( // default voltage range is +/- 5V
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.ADC_DATA_WIDTH(ADC_DATA_WIDTH)
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) virtual_adc (
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.clk_i(clk_adc),
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.voltage_i(signal_voltage),
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.otr_o(adc_otr),
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.data_o(adc_data)
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);
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//------------------------------------------------------------
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// Statistics processing
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//------------------------------------------------------------
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//------------------------------------------------------------
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// Config handler
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//------------------------------------------------------------
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//------------------------------------------------------------
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// DUT
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//------------------------------------------------------------
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reflectometer_top #(
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.DAC_DATA_WIDTH(DAC_DATA_WIDTH),
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.ADC_DATA_WIDTH(ADC_DATA_WIDTH),
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.PACK_FACTOR(PACK_FACTOR),
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.PROCESS_MODE(PROCESS_MODE),
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.ZERO_LEVEL(ZERO_LEVEL),
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.ACCUM_WIDTH(ACCUM_WIDTH),
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.N_MAX(N_MAX),
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.PACKET_SIZE(PACKET_SIZE)
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) DUT (
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.clk_in(clk_ref),
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.rst_n(rst_n),
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// Status
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.locked(mmcm_locked),
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.workflow_done(workflow_done),
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.processing_done(processing_done),
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// Accumulator AXI-S bus
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.clk_axis_accumulator(clk_eth_phy), // GMII PHY RX clock
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.axis_accumulator(axis_accumulator_if.master),
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// Control AXI-S bus
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.clk_axis_control(clk_eth_phy), // GMII PHY TX clock
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.axis_control(axis_control_if.slave),
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.window_size(window_size_port), // direct signal crutch (old controller)
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// RTL-MAC handshake
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.request_ready(request_ready),
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.send_request(send_request),
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// DAC
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.dac_clk_o(clk_dac),
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.dac_data(dac_data),
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.dac_wrt(dac_wrt),
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// ADC
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.adc_clk_o(clk_adc),
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.adc_data(adc_data),
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.adc_otr(adc_otr)
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);
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//------------------------------------------------------------
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// Тактовые сигналы
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//------------------------------------------------------------
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initial begin
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forever #(CLK_REF_PERIOD/2) clk_ref = ~clk_ref;
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end
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initial begin
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forever #(CLK_ETH_PHY_PERIOD/2) clk_eth_phy = ~clk_eth_phy;
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end
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//------------------------------------------------------------
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// Таски для тестирования
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//------------------------------------------------------------
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// Таски работы с AXI-Stream
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task automatic dut_soft_reset(virtual axis_if#(8).tb vif);
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logic [7:0] tx_packet[];
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tx_packet = '{8'h0f};
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vif.master_send(tx_packet);
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endtask
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task automatic dut_start(virtual axis_if#(8).tb vif);
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logic [7:0] tx_packet[];
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tx_packet = '{8'hf0};
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vif.master_send(tx_packet);
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endtask
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task automatic dut_send_system_config(
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virtual axis_if#(8).tb vif,
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input logic [31:0] pulse_width,
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input logic [31:0] pulse_period,
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input logic [15:0] pulse_num,
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input logic [13:0] pulse_height, // achtung! p_height strictly must have 14 bits of width
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input logic [31:0] pulse_period_adc,
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input logic [31:0] window_size
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);
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// Создаем временный фиксированный массив и упаковываем всё одной строкой
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logic [7:0] tx_packet[];
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// Ахтунг, 14-битный ЦАП захардкожен
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if (DAC_DATA_WIDTH != 14)
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$warning("[WARNING] -dut_send_system_config- Default pulse height (DAC bitwidth) is equal to 14. Be aware, controller packet structure is coded for 14 bits");
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tx_packet = '{
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8'h88, // Команда
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pulse_width[7:0], pulse_width[15:8], pulse_width[23:16], pulse_width[31:24],
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pulse_period[7:0], pulse_period[15:8], pulse_period[23:16], pulse_period[31:24],
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pulse_num[7:0], pulse_num[15:8], pulse_height[7:0], 8'({2'b00, pulse_height[13:8]}),
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pulse_period_adc[7:0], pulse_period_adc[15:8], pulse_period_adc[23:16], pulse_period_adc[31:24]
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};
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vif.master_send(tx_packet);
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// TODO remove for new controller
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window_size_port = window_size;
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endtask
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// Таски сбора статистики
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task automatic dut_read_output(
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virtual axis_if#(8).tb vif,
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input int sample_num,
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input int window_size,
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input bit randomize_recv_delays,
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output int output_data[]
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);
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logic [7:0] rx_packet[];
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logic [ACCUM_WIDTH-1:0] data_packet[];
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int numbers_per_packet = PACKET_SIZE/(ACCUM_WIDTH/8);
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int packet_num = $ceil(real'(sample_num / window_size) / real'(numbers_per_packet));
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int timeout_flag = 0;
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int packet_counter = 0;
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if (sample_num % window_size) begin
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$error("-dut_read_output- Sample_num must be multiple of window_size: %0d %% %0d = %0d", sample_num, window_size, sample_num % window_size);
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$finish;
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end
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data_packet = new[numbers_per_packet];
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output_data = new[numbers_per_packet * packet_num];
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// count send_request pulses (equal to number of packets)
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fork
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begin : packet_counter_proc
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forever begin
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@(posedge clk_eth_phy);
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if(send_request === 1)
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packet_counter++;
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end
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end
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join_none
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// Wait until reflectometer done sampling and averaging
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wait(processing_done == 1);
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// recv loop
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// если число пакетов превышает заложенное предрассчитанное значение -- ошибка
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fork : recv_loop_proc
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begin
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// packet recv loop
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forever begin
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if (packet_counter > packet_num) begin
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$error("-dut_read_output- Packet overflow detected. Number of data packets exceeds expected amount of packets");
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$finish;
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end
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if (randomize_recv_delays)
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repeat($urandom_range(0, 500)) @(posedge clk_eth_phy);
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timeout_flag = 0;
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fork : receive_packet_timeout
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begin
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request_ready = 1;
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vif.slave_recv(rx_packet);
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request_ready = 0;
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end
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begin
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repeat(REQUEST_TIMEOUT) @(posedge clk_eth_phy);
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timeout_flag = 1;
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end
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join_any
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disable receive_packet_timeout;
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if (timeout_flag) begin
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$error("-dut_read_output- Timeout detected when receiving packet");
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$finish;
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end
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if (rx_packet.size() != PACKET_SIZE) begin
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$error("-dut_read_output- Wrong packet size received: %0d bytes received, %0d bytes expected", rx_packet.size(), PACKET_SIZE);
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$finish;
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end
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// unpack values
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data_packet = {<< byte {rx_packet}};
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data_packet = {<< ACCUM_WIDTH {data_packet}};
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// copy and convert values
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for (int j = 0; j < data_packet.size(); j++) begin
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output_data[(packet_counter-1) * data_packet.size() + j] = int'(data_packet[j]);
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end
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end
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end
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begin
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// IP workflow completion event
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wait(workflow_done == 1);
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end
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join_any
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disable recv_loop_proc;
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disable packet_counter_proc;
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if (packet_counter != packet_num) begin
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$error("-dut_read_output- Wrong number of packets received: %0d received, %0d expected", packet_counter, packet_num);
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$finish;
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end
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endtask
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//------------------------------------------------------------
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// Функции и таски для верификации сигналов
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//------------------------------------------------------------
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// Таска генерации идеального тестового сигнала
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task automatic reference_signal(
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input int pulse_width,
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input int pulse_height,
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input int pulse_period_adc,
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input int window_size,
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output real result[]
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);
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/*
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Globals:
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ADC and DAC clock periods,
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Virtual ADC and DAC voltage steps
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Task developed with assumption that first discrete values of DAC and ADC
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are syncrhonized at t==0 and started simultaneously.
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Gains and biases of virtual ADC & DAC are default and ranges are [-5V;5V].
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Bitwidths may be altered.
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Returned result[] array is an array of sums of voltage potentials in discrete time points.
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Discrete samples summed over a time window.
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result[time] = (voltage)
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*/
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int sample_num = pulse_period_adc / window_size; // total averaged output samples from accumulator
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real current_signal_sample, partial_sum;
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real ref_signal_active_voltage = virtual_dac.code_to_voltage(pulse_height);
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real ref_signal_zero_voltage = virtual_dac.code_to_voltage(ZERO_LEVEL);
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if (pulse_period_adc % window_size) begin
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$error("-reference_signal- pulse_period_adc must be multiple of window_size: %0d %% %0d = %0d", pulse_period_adc, window_size, pulse_period_adc % window_size);
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$finish;
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end
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result = new[sample_num];
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partial_sum = 0;
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for (int i = 0; i < pulse_period_adc; i++) begin
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// var i in ADC timespace
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// i == 0 is a t0 of pulse generation and sampling
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current_signal_sample = (i*CLK_ADC_PERIOD <= pulse_width*CLK_DAC_PERIOD) ? ref_signal_active_voltage : ref_signal_zero_voltage;
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partial_sum += current_signal_sample;
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if (i % window_size == (window_size-1)) begin
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result[i / window_size] = partial_sum;
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partial_sum = 0;
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end
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end
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endtask
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// Функция проверки размеров выборок
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function automatic void check_size(
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input real a[],
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input real b[]
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);
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if (a.size() != b.size())
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$fatal(1, "Array size mismatch: %0d != %0d",
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a.size(), b.size());
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if (a.size() == 0)
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$error(1, "Empty array");
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endfunction
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// Среднее по выборке
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function automatic real array_mean(
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input real a[]
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);
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real sum = 0.0;
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foreach (a[i])
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sum += a[i];
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return sum / a.size();
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endfunction
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// MSE двух выборок
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function automatic real calc_mse(
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input real a[],
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input real b[]
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);
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real sum = 0.0;
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check_size(a, b);
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foreach (a[i]) begin
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real err;
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err = a[i] - b[i];
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sum += err * err;
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end
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return sum / a.size();
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endfunction
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// NRMSE двух выборок (нормирование MSE)
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function automatic real calc_nrmse(
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input real a[],
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input real b[]
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);
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real mse;
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real min_val;
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real max_val;
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mse = calc_mse(a, b);
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min_val = a[0];
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max_val = a[0];
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foreach (a[i]) begin
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if (a[i] < min_val)
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min_val = a[i];
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if (a[i] > max_val)
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max_val = a[i];
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end
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if (max_val == min_val)
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return 0.0;
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return $sqrt(mse) / (max_val - min_val);
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endfunction
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// Функция модуля
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function automatic real abs_f(input real x);
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return (x < 0.0) ? -x : x;
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endfunction
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// Максимальная абсолютная ошибка
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function automatic real calc_max_error(
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input real a[],
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input real b[]
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);
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real max_err = 0.0;
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check_size(a, b);
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foreach (a[i]) begin
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real err;
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err = abs_f(a[i] - b[i]);
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if (err > max_err)
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max_err = err;
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end
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return max_err;
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endfunction
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// Коэффициент корреляции Пирсона
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function automatic real calc_pearson(
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input real a[],
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input real b[]
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);
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real mean_a;
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real mean_b;
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real numerator = 0.0;
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real denom_a = 0.0;
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real denom_b = 0.0;
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check_size(a, b);
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mean_a = array_mean(a);
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mean_b = array_mean(b);
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foreach (a[i]) begin
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real da;
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real db;
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da = a[i] - mean_a;
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db = b[i] - mean_b;
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numerator += da * db;
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denom_a += da * da;
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denom_b += db * db;
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end
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if ((denom_a == 0.0) || (denom_b == 0.0))
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return 0.0;
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return numerator / $sqrt(denom_a * denom_b);
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endfunction
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// Вспомогательная функция для вывода массива
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function automatic void display_array_f(input real a[]);
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$write("\t");
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foreach(a[i])
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$write("%f ", a[i]);
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$write("\n");
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endfunction
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// Основная таска типового теста
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task automatic run_test_case(
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virtual axis_if#(8).tb ctrl_vif,
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virtual axis_if#(8).tb accum_vif,
|
||
input int pulse_width,
|
||
input int pulse_period,
|
||
input int pulse_num,
|
||
input int pulse_height,
|
||
input int pulse_period_adc,
|
||
input int window_size,
|
||
input bit rand_recv_delays,
|
||
input bit use_reset,
|
||
output bit result
|
||
);
|
||
int output_data[]; // raw accum values
|
||
real output_signal_v[]; // accum values after voltage conversion
|
||
real reference_signal_v[]; // reference signal voltage values
|
||
real nrmse, pearson, max_err; // error and correlation metrics
|
||
|
||
if (use_reset) begin
|
||
dut_soft_reset(ctrl_vif);
|
||
#100;
|
||
end
|
||
|
||
dut_send_system_config(
|
||
.vif(ctrl_vif),
|
||
.pulse_width(pulse_width),
|
||
.pulse_period(pulse_period),
|
||
.pulse_num(pulse_num),
|
||
.pulse_height(pulse_height),
|
||
.pulse_period_adc(pulse_period_adc),
|
||
.window_size(window_size)
|
||
);
|
||
#100;
|
||
|
||
dut_start(ctrl_vif);
|
||
|
||
dut_read_output(
|
||
.vif(accum_vif),
|
||
.sample_num(pulse_period_adc),
|
||
.window_size(window_size),
|
||
.randomize_recv_delays(rand_recv_delays),
|
||
.output_data(output_data)
|
||
);
|
||
// actual size of payload is pulse_period_adc / window_size
|
||
output_signal_v = new[pulse_period_adc / window_size];
|
||
|
||
// voltage conversion
|
||
begin
|
||
// zero level for partial sum
|
||
real zero_level_bias = window_size * virtual_adc.ZERO_CODE;
|
||
// common voltage multiplier for step & amplifier
|
||
real voltage_multiplier = virtual_adc.VOLTAGE_STEP / virtual_adc.VOLTAGE_GAIN;
|
||
// array conversion
|
||
foreach (output_signal_v[i]) begin
|
||
real average_code_per_pulse = real'(output_data[i]) / pulse_num;
|
||
output_signal_v[i] = (average_code_per_pulse - zero_level_bias) * voltage_multiplier;
|
||
end
|
||
end
|
||
|
||
reference_signal(
|
||
.pulse_width(pulse_width),
|
||
.pulse_height(pulse_height),
|
||
.pulse_period_adc(pulse_period_adc),
|
||
.window_size(window_size),
|
||
.result(reference_signal_v)
|
||
);
|
||
|
||
`ifdef DEBUG
|
||
$display("[TB] Output signal");
|
||
display_array_f(output_signal_v);
|
||
$display("[TB] Reference signal");
|
||
display_array_f(reference_signal_v);
|
||
`endif
|
||
|
||
nrmse = calc_nrmse(output_signal_v, reference_signal_v);
|
||
pearson = calc_pearson(output_signal_v, reference_signal_v);
|
||
max_err = calc_max_error(output_signal_v, reference_signal_v);
|
||
|
||
`ifdef DEBUG
|
||
$display("[TB] Metrics:\n\tNRMSE = %0.4f\t|\tPearson = %0.4f\t|\tMax error = %0.4f", nrmse, pearson, max_err);
|
||
`endif
|
||
|
||
// check metrics
|
||
result = 1;
|
||
if (pearson < 0.99)
|
||
result = 0;
|
||
if (nrmse > 0.1)
|
||
result = 0;
|
||
/*
|
||
Max error not used in evaluation because of fast pulse edge falling
|
||
resulting in plain difference between active signal level and zero level
|
||
For ex.: zero_level = 0x00 = -5V. pulse_height = 2^14-1 = 0x3fff = 5V
|
||
In some cases like jitter this may cause max error = 5 - (-5) = 10(V)
|
||
This cases are hardly traceble, thus max error not used in eval.
|
||
*/
|
||
endtask
|
||
|
||
//------------------------------------------------------------
|
||
// ОСНОВНОЙ ПРОЦЕСС ТЕСТИРОВАНИЯ
|
||
//------------------------------------------------------------
|
||
initial begin
|
||
bit result_flag;
|
||
int total_failed_tests = 0, total_tests = 0;
|
||
|
||
automatic virtual axis_if.tb control_vif = axis_control_if.tb;
|
||
automatic virtual axis_if.tb accumulator_vif = axis_accumulator_if.tb;
|
||
|
||
$info("[TB] DUT initializaton");
|
||
// Инициализация
|
||
request_ready = 0;
|
||
rst_n = 0;
|
||
#100;
|
||
rst_n = 1;
|
||
wait(mmcm_locked === 1'b1);
|
||
#150;
|
||
$info("[TB] MMCM locked");
|
||
|
||
// Meause periods because actual values hardcoded in IP
|
||
fork
|
||
`MEASURE_CLK(DUT.clk_sampler, CLK_ADC_PERIOD);
|
||
`MEASURE_CLK(DUT.clk_generator, CLK_DAC_PERIOD);
|
||
join
|
||
$info("[TB] ADC & DAC clock periods measured: ADC_period = %0.3f, DAC_period = %0.3f", CLK_ADC_PERIOD, CLK_DAC_PERIOD);
|
||
|
||
dut_soft_reset(control_vif);
|
||
#100;
|
||
|
||
// Тесты
|
||
$info("[TB] Tests start");
|
||
|
||
$info("[TB] Simple test run");
|
||
|
||
run_test_case(
|
||
.ctrl_vif(control_vif),
|
||
.accum_vif(accumulator_vif),
|
||
.pulse_width(400),
|
||
.pulse_period(1000),
|
||
.pulse_num(5),
|
||
.pulse_height(12000),
|
||
.pulse_period_adc(600),
|
||
.window_size(10),
|
||
.rand_recv_delays(0),
|
||
.use_reset(0),
|
||
.result(result_flag)
|
||
);
|
||
|
||
$info("[TB] Random test run");
|
||
|
||
$info("[TB] Corner case test run");
|
||
|
||
|
||
// if (!failed)
|
||
$info("[TB] ALL PASSED");
|
||
$finish;
|
||
end
|
||
endmodule
|