88 lines
2.8 KiB
Systemverilog
88 lines
2.8 KiB
Systemverilog
`timescale 1ns / 1ps
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module generator
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#(
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parameter DATA_WIDTH = 14,
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parameter ZERO_LEVEL = 8192 // 8192 or 0
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)
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(
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input clk_dac,
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input rst,
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input start,
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input [31:0] pulse_width,
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input [31:0] pulse_period,
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input [DATA_WIDTH-1:0] pulse_height,
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input [15:0] pulse_num,
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input request,
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output logic [DATA_WIDTH-1:0] dac_out,
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output logic done
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);
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logic [DATA_WIDTH-1:0] pulse_height_reg;
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logic [31:0] pulse_width_reg, pulse_period_reg;
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logic [15:0] pulse_num_reg;
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logic [15:0] cnt_pulse_num;
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logic [31:0] cnt_pulse_period;
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logic enable, synced;
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always @(posedge clk_dac) begin
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if (rst) begin
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pulse_height_reg <= ZERO_LEVEL;
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pulse_width_reg <= 0;
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pulse_period_reg <= 0;
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pulse_num_reg <= 0;
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cnt_pulse_num <= 0;
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cnt_pulse_period <= 0;
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dac_out <= ZERO_LEVEL;
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done <= 0;
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enable <= 0;
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synced <= 0;
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end
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else begin
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// wait start for updating registers
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if (start & !enable) begin
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enable <= 1;
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pulse_width_reg <= pulse_width;
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pulse_period_reg <= pulse_period;
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pulse_num_reg <= pulse_num;
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pulse_height_reg <= pulse_height;
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end
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// main work cycle
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if (enable) begin
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if (cnt_pulse_num != pulse_num_reg) begin
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// wait for synchronization with sampler
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if (!synced) begin
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if (request & done) begin
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synced <= 1;
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done <= 0;
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end
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else
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done <= 1;
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end
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else begin
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if (cnt_pulse_period != pulse_period_reg) begin
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if (cnt_pulse_period < pulse_width_reg)
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dac_out <= pulse_height_reg;
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else
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dac_out <= ZERO_LEVEL;
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cnt_pulse_period++;
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end
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else begin
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cnt_pulse_num++;
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cnt_pulse_period <= 0;
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synced <= 0;
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dac_out <= ZERO_LEVEL;
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end
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end
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end
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else begin
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cnt_pulse_num <= 0;
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enable <= 0;
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end
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end
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end
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end
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endmodule
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