335 lines
12 KiB
Systemverilog
335 lines
12 KiB
Systemverilog
module out_axis_fifo #(
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parameter ACCUM_WIDTH = 32,
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parameter RW_WIDTH = 32,
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parameter PACKET_SIZE = 256
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) (
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input logic dma_clk_in,
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input logic acc_clk_in,
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input logic rst,
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input logic [31:0] smp_num,
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input logic [31:0] window_size,
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// AXI stream master for output, dma_clk_in domain
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output logic [RW_WIDTH-1:0] m_axis_tdata,
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output logic m_axis_tvalid,
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input logic m_axis_tready,
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output logic m_axis_tlast,
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// eth handshake
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input logic req_ready,
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output logic send_req,
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output logic [15:0] udp_data_length,
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// data from acc
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input logic [ACCUM_WIDTH-1:0] acc_din,
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input logic din_valid,
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// input pulse
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input logic readout_begin,
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// output pulses
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output logic batch_req,
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output logic finish
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);
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// sync reset
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reg [1:0] rst_sync_ff;
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reg rst_eth;
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always @(posedge acc_clk_in or posedge rst) begin
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if (rst) begin
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rst_sync_ff <= 2'b11;
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end else begin
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rst_sync_ff <= {rst_sync_ff[0], 1'b0};
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end
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end
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assign rst_eth = rst_sync_ff[1];
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logic [1:0] rst_acc_ff;
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logic rst_acc;
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always_ff @(posedge acc_clk_in or posedge rst) begin
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if (rst)
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rst_acc_ff <= 2'b11;
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else
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rst_acc_ff <= {rst_acc_ff[0], 1'b0};
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end
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assign rst_acc = rst_acc_ff[1];
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// fifo params calc
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// round up to be enough for 2xPACKET_SIZE storage
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localparam int MIN_BYTES = 2 * PACKET_SIZE;
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localparam int MIN_BITS = MIN_BYTES * 8;
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localparam int MIN_WR_WORDS = (MIN_BITS + ACCUM_WIDTH - 1) / ACCUM_WIDTH; // ceil div
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localparam int WDEPTH_BITS = $clog2(MIN_WR_WORDS);
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localparam int FIFO_WDEPTH = 1 << WDEPTH_BITS;
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localparam int FIFO_RDEPTH = FIFO_WDEPTH * ACCUM_WIDTH / RW_WIDTH;
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localparam int RDEPTH_BITS = $clog2(FIFO_RDEPTH) + 1;
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localparam int WR_WORD_BYTES = ACCUM_WIDTH/8;
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localparam int RD_WORD_BYTES = RW_WIDTH/8;
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localparam int PACKET_WR_WORDS = PACKET_SIZE / WR_WORD_BYTES;
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localparam int PACKET_RD_WORDS = PACKET_SIZE / RD_WORD_BYTES;
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wire wr_unavail;
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wire wr_rst_busy;
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reg rd_en;
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typedef enum logic [2:0] {
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WR_IDLE = 3'd0,
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WR_CHECK = 3'd1,
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WR_RUN = 3'd2,
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WR_END = 3'd3
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} wr_state_t;
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(* MARK_DEBUG="true" *) wr_state_t wr_state;
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// Write FSM
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reg [31:0] wr_cnt; // current BIT mem ptr
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reg [31:0] wr_batch_tgt; // next 'target' that should be written from batch
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reg [31:0] wr_total; // total BITS to be sent!
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logic [31:0] window_size_reg;
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wire [31:0] window_size_safe = (window_size == 32'd0) ? 32'd1 : window_size;
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wire empty;
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wire [WDEPTH_BITS:0] wr_data_count;
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// NOTE:
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// each written "acc_din" ACCUM_WIDTH word
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// is counted as window_size samples actually
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// because hw division for counters is painful
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// so we just increased the counter sizes
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always_ff @(posedge acc_clk_in) begin
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if (rst_acc) begin
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wr_state <= WR_IDLE;
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wr_cnt <= 32'b0;
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wr_batch_tgt <= 32'b0;
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wr_total <= 32'b0;
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window_size_reg <= 32'd1;
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batch_req <= 0;
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finish <= 0;
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end else begin
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case (wr_state)
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// wait until readout is requested
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WR_IDLE: begin
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if (readout_begin) begin
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wr_cnt <= 32'b0;
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wr_state <= WR_CHECK;
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wr_total <= smp_num * ACCUM_WIDTH;
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wr_batch_tgt <= 32'b0;
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window_size_reg <= window_size_safe;
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batch_req <= 0;
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finish <= 0;
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end
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end
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// wait until we can request a word
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// depends on prog_full signal
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WR_CHECK: begin
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if ((wr_data_count < (FIFO_WDEPTH - PACKET_WR_WORDS)) && ~wr_rst_busy) begin
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batch_req <= 1;
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// should give us exactly PACKET_SIZE * 8 bits
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// multiplied by window_size, because we count
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// each given ACCUM_WIDTH word as window_size samples !!!
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wr_batch_tgt <= wr_batch_tgt + (8 * window_size_reg * PACKET_SIZE);
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wr_state <= WR_RUN;
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end else begin
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batch_req <= 0;
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end
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end
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// wait until all requested packet is written
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WR_RUN: begin
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batch_req <= 0;
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if (wr_cnt == wr_batch_tgt) begin
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// got enough words
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wr_state <= WR_END;
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end else if (wr_cnt > wr_batch_tgt) begin
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// weird case when accum gave us too much words
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// block resets
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wr_cnt <= 32'hffffffff; // sort of signal for sim/ila
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wr_state <= WR_END;
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end
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if (din_valid) begin
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// data supplied
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// count as we got window_size samples
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wr_cnt <= wr_cnt + ACCUM_WIDTH * window_size_reg;
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end
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end
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// check if this was last data batch
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WR_END: begin
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// here we check that we sent enough data
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// wr_cnt should be by design PACKET_SIZE-aligned
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if (wr_cnt >= wr_total) begin
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// wait until all data is sent
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if (empty) begin
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finish <= 1;
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wr_state <= WR_IDLE;
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end
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end else begin
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// next word
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wr_state <= WR_CHECK;
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end
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end
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endcase
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end
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end
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// Readout FSM with ethernet request
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assign udp_data_length = PACKET_SIZE; // fixed packet size
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reg [15:0] sent_cnt;
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typedef enum logic [2:0] {
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RD_IDLE = 3'd0,
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RD_CHECK = 3'd1,
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RD_SEND = 3'd2
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} rd_state_t;
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(* MARK_DEBUG="true" *) rd_state_t rd_state;
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wire rd_valid;
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wire [RDEPTH_BITS-1:0] rd_data_count;
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always_ff @(posedge dma_clk_in) begin
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if (rst_eth) begin
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rd_state <= RD_IDLE;
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send_req <= 1'b0;
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sent_cnt <= 16'd0;
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m_axis_tlast <= 1'b0;
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m_axis_tvalid <= 1'b0;
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rd_en <= 1'b0;
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end else begin
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case (rd_state)
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// wait until fifo has enough data to send
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RD_IDLE: begin
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if (rd_data_count >= PACKET_RD_WORDS) begin
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// enough data to send packet, begin
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rd_state <= RD_CHECK;
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end
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send_req <= 1'b0;
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sent_cnt <= 16'd0;
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rd_en <= 1'b0;
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m_axis_tlast <= 1'b0;
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m_axis_tvalid <= 1'b0;
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end
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// await udp ready
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RD_CHECK: begin
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if (req_ready) begin
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send_req <= 1'b1;
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rd_state <= RD_SEND;
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end
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end
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// send data
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RD_SEND: begin
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// udp is ready and fifo is ready = sent
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send_req <= 1'b0;
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if (m_axis_tready && rd_valid) begin
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rd_en <= 1'b1;
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m_axis_tvalid <= 1'b1;
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sent_cnt <= sent_cnt + 1;
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// final packet of the batch
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if (sent_cnt == PACKET_RD_WORDS-1) begin
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rd_state <= RD_IDLE;
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m_axis_tlast <= 1'b1;
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end
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end else begin
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rd_en <= 1'b0;
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m_axis_tvalid <= 1'b0;
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end
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end
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endcase
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end
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end
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logic [ACCUM_WIDTH-1:0] fifo_din_r, acc_din_reg, din_valid_reg;
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logic fifo_wr_en_r;
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always_ff @(posedge acc_clk_in) begin
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if (rst_acc) begin
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fifo_din_r <= '0;
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fifo_wr_en_r <= 1'b0;
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din_valid_reg <= 1'b0;
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end else begin
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fifo_wr_en_r <= 1'b0;
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acc_din_reg <= acc_din;
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if (!wr_rst_busy && din_valid_reg) begin
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fifo_din_r <= acc_din_reg;
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fifo_wr_en_r <= 1'b1;
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end
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din_valid_reg <= din_valid;
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end
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end
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// xpm_fifo_async: Asynchronous FIFO
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// Xilinx Parameterized Macro, version 2025.1
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xpm_fifo_async #(
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.DOUT_RESET_VALUE("0"), // String
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.FIFO_READ_LATENCY(1), // DECIMAL
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.FIFO_WRITE_DEPTH(FIFO_WDEPTH),
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.FULL_RESET_VALUE(0),
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.PROG_EMPTY_THRESH(PACKET_RD_WORDS),
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.PROG_FULL_THRESH(PACKET_WR_WORDS),
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.RD_DATA_COUNT_WIDTH(RDEPTH_BITS),
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.READ_DATA_WIDTH(RW_WIDTH), // always 8 bit for eth
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.READ_MODE("fwft"),
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.SIM_ASSERT_CHK(1), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
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.USE_ADV_FEATURES("1616"), // String
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.WRITE_DATA_WIDTH(ACCUM_WIDTH),
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.WR_DATA_COUNT_WIDTH(WDEPTH_BITS+1)
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)
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xpm_fifo_async_inst (
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.data_valid(rd_valid), // 1-bit output: Read Data Valid: When asserted, this signal indicates that valid data is available on the
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// output bus (dout).
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.dout(m_axis_tdata),
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.empty(empty),
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.full( ),
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.prog_full(wr_unavail), // 1-bit output: Programmable Full: This signal is asserted when the number of words in the FIFO is greater than
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// or equal to the programmable full threshold value. It is de-asserted when the number of words in the FIFO is
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// less than the programmable full threshold value.
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.rd_data_count(rd_data_count), // RD_DATA_COUNT_WIDTH-bit output: Read Data Count: This bus indicates the number of words read from the FIFO.
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.wr_data_count(wr_data_count), // WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus indicates the number of words written into the
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// FIFO.
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.rd_clk(dma_clk_in), // 1-bit input: Read clock: Used for read operation. rd_clk must be a free running clock.
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.rd_en(rd_en), // 1-bit input: Read Enable: If the FIFO is not empty, asserting this signal causes data (on dout) to be read
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// from the FIFO. Must be held active-low when rd_rst_busy is active high.
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.rst(rst),
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.din(fifo_din_r), // WRITE_DATA_WIDTH-bit input: Write Data: The input data bus used when writing the FIFO.
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.wr_clk(acc_clk_in), // 1-bit input: Write clock: Used for write operation. wr_clk must be a free running clock.
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.wr_en(fifo_wr_en_r),
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.wr_rst_busy(wr_rst_busy)
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);
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endmodule |