Files
reflectometer_fpga_project/designs/full_new_reflectometer/tests/test_timing.xdc
T

7 lines
323 B
Tcl

# Primary clocks
create_clock -name ref_clock -period 5.000 [get_ports ctrl_clk]
set clk_125_name [get_clocks -of_objects [get_pins generator_inst/clk_dac_125]]
set clk_65_name [get_clocks -of_objects [get_pins accumulator_top_inst/clk_adc_65]]
set_clock_groups -asynchronous -group $clk_125_name -group $clk_65_name